[llvm-commits] [llvm] r60583 - /llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp

[Dan Gohman]

Author: djg
Date: Thu Dec  4 23:30:02 2008
New Revision: 60583

URL: http://llvm.org/viewvc/llvm-project?rev=60583&view=rev
Log:
Ignore IMPLICIT_DEF instructions when computing physreg liveness.
While they appear to provide a normal clobbering def, they don't
in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It
would be good to change INSERT_SUBREG; until then, this change
allows post-regalloc scheduling to cope in a mildly conservative
way.

Modified:
    llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp

Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=60583&r1=60582&r2=60583&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Dec  4 23:30:02 2008
@@ -353,6 +353,13 @@
        I != E; ++I, --Count) {
     MachineInstr *MI = &*I;
 
+    // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
+    // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
+    // is left behind appearing to clobber the super-register, while the
+    // subregister needs to remain live. So we just ignore them.
+    if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+      continue;
+
     // Check if this instruction has an anti-dependence that we're
     // interested in.
     DenseMap<MachineInstr *, unsigned>::iterator C = CriticalAntiDeps.find(MI);