[llvm-commits] [llvm] r55892 - /llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

[Evan Cheng]

Author: evancheng
Date: Mon Sep  8 03:38:20 2008
New Revision: 55892

URL: http://llvm.org/viewvc/llvm-project?rev=55892&view=rev
Log:
Add fast isel physical register definition support.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=55892&r1=55891&r2=55892&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Sep  8 03:38:20 2008
@@ -576,7 +576,16 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0);
+  else {
+    BuildMI(MBB, II).addReg(Op0);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
+
   return ResultReg;
 }
 
@@ -586,7 +595,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addReg(Op1);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -596,7 +613,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addImm(Imm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -606,7 +631,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -616,7 +649,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -626,7 +667,15 @@
   unsigned ResultReg = createResultReg(RC);
   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
   
-  BuildMI(MBB, II, ResultReg).addImm(Imm);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addImm(Imm);
+  else {
+    BuildMI(MBB, II).addImm(Imm);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }
 
@@ -637,6 +686,14 @@
   unsigned ResultReg = createResultReg(SRC);
   const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
   
-  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
+  if (II.getNumDefs() >= 1)
+    BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
+  else {
+    BuildMI(MBB, II).addReg(Op0).addImm(Idx);
+    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+                                         II.ImplicitDefs[0], RC, RC);
+    if (!InsertedCopy)
+      ResultReg = 0;
+  }
   return ResultReg;
 }