[llvm-commits] [llvm] r54229 - in /llvm/trunk/lib/Target/Mips: MipsISelLowering.cpp MipsInstrFPU.td

[Bruno Cardoso Lopes]

Author: bruno
Date: Wed Jul 30 14:00:31 2008
New Revision: 54229

URL: http://llvm.org/viewvc/llvm-project?rev=54229&view=rev
Log:
Added pattern for floating point zero immediate (avoiding a constant pool
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrFPU.td

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=54229&r1=54228&r2=54229&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jul 30 14:00:31 2008
@@ -77,6 +77,9 @@
   } else 
     addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
 
+  // Legal fp constants
+  addLegalFPImmediate(APFloat(+0.0f));
+
   // Load extented operations for i1 types must be promoted 
   setLoadXAction(ISD::EXTLOAD,  MVT::i1,  Promote);
   setLoadXAction(ISD::ZEXTLOAD, MVT::i1,  Promote);

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=54229&r1=54228&r2=54229&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed Jul 30 14:00:31 2008
@@ -194,13 +194,13 @@
                   "mfc1 $rt, $fs", []>;
 
   def MTC1  : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
-                  "mtc1 $fs, $rt", []>;
+                  "mtc1 $rt, $fs", []>;
 
   def MFC1A : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins AFGR32:$fs),
                   "mfc1 $rt, $fs", []>;
 
   def MTC1A : FFR<0x11, 0x00, 0x04, (outs AFGR32:$fs), (ins CPURegs:$rt),
-                  "mtc1 $fs, $rt", []>;
+                  "mtc1 $rt, $fs", []>;
 }
 
 /// Floating Point Memory Instructions
@@ -324,8 +324,18 @@
 //===----------------------------------------------------------------------===//
 // Floating Point Patterns
 //===----------------------------------------------------------------------===//
+def fpimm0 : PatLeaf<(fpimm), [{
+  return N->isExactlyValue(+0.0);
+}]>;
+
+def : Pat<(f32 fpimm0), (MTC1 ZERO)>, Requires<[IsSingleFloat]>;
+def : Pat<(f32 fpimm0), (MTC1A ZERO)>, Requires<[In32BitMode]>;
+
 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
+
 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_SO32 FGR32:$src))>;
-def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1 (TRUNC_W_AS32 AFGR32:$src))>;
+def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1A (TRUNC_W_AS32 AFGR32:$src))>;
 
+def : Pat<(i32 (bitconvert FGR32:$src)),  (MFC1 FGR32:$src)>;
+def : Pat<(i32 (bitconvert AFGR32:$src)), (MFC1A AFGR32:$src)>;