[llvm-commits] [llvm] r53146 - in /llvm/trunk/lib/Target/Mips: Mips.td MipsAsmPrinter.cpp MipsCallingConv.td MipsISelDAGToDAG.cpp MipsISelLowering.cpp MipsISelLowering.h MipsInstrFPU.td MipsInstrFormats.td MipsInstrInfo.cpp MipsInstrInfo.h MipsInstrInfo.td MipsMachineFunction.h MipsRegisterInfo.cpp MipsRegisterInfo.td MipsSubtarget.cpp MipsSubtarget.h MipsTargetMachine.cpp

[Eric Christopher]

Couple of questions:

+  if (!Subtarget->isAllegrex()) {
+    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
+    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
+  }

What's Allegrex specific here... Aaah. From looking later it looks  
like SEH and SEB. A suggestion would be to have Subtarget- 
 >hasSEBandSEH or something. Other targets have these as well.

+// Float Point Instructions

"Floating"

+    Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2

and Mips64, Mips64r2 :)

+  bool hasAllegrexVFPU() const { return HasAllegrexVFPU; };
+  bool isAllegrex() const { return IsAllegrex; };

For these it's probably best to return depending on CPU feature not  
necessarily cpu type. There's a lot of commonality between mips chips.

Otherwise it looked good from what I can tell. Great job!

-eric