[llvm-commits] [llvm] r48279 - in /llvm/trunk/lib: CodeGen/SelectionDAG/DAGCombiner.cpp Target/X86/X86InstrMMX.td Target/X86/X86InstrSSE.td

[Chris Lattner]

On Mar 12, 2008, at 12:02 AM, Evan Cheng wrote:

> Author: evancheng
> Date: Wed Mar 12 02:02:50 2008
> New Revision: 48279
>
> URL: http://llvm.org/viewvc/llvm-project?rev=48279&view=rev
> Log:
> Clean up my own mess.
> X86 lowering normalize vector 0 to v4i32. However DAGCombine can  
> fold (sub x, x) -> 0 after legalization. It can create a zero vector  
> of a type that's not expected (e.g. v8i16). We don't want to disable  
> the optimization since leaving a (sub x, x) is really bad. Add isel  
> patterns for other types of vector 0 to ensure correctness. It's  
> highly unlikely to happen other than in bugpoint reduced test cases.

Does this make the V_SET0's with the canonical result type?  If so,  
they will be CSEd during isel.

-Chris