[llvm-commits] [llvm] r48205 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Author: lattner
Date: Mon Mar 10 19:59:28 2008
New Revision: 48205

URL: http://llvm.org/viewvc/llvm-project?rev=48205&view=rev
Log:
If a register operand comes from the variadic part of a node, don't
verify the register constraint matches what the instruction expects.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=48205&r1=48204&r2=48205&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Mon Mar 10 19:59:28 2008
@@ -531,14 +531,16 @@
     
     // Verify that it is right.
     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+#ifndef NDEBUG
     if (II) {
+      // There may be no register class for this operand if it is a variadic
+      // argument (RC will be NULL in this case).  In this case, we just assume
+      // the regclass is ok.
       const TargetRegisterClass *RC =
                           getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
-      assert(RC && "Don't have operand info for this instruction!");
       const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
-      if (VRC != RC) {
+      if (RC && VRC != RC) {
         cerr << "Register class of operand and regclass of use don't agree!\n";
-#ifndef NDEBUG
         cerr << "Operand = " << IIOpNum << "\n";
         cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
         cerr << "MI = "; MI->print(cerr);
@@ -547,11 +549,11 @@
              << ", align = " << VRC->getAlignment() << "\n";
         cerr << "Expected RegClass size = " << RC->getSize()
              << ", align = " << RC->getAlignment() << "\n";
-#endif
         cerr << "Fatal error, aborting.\n";
         abort();
       }
     }
+#endif
   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
     MI->addOperand(MachineOperand::CreateImm(C->getValue()));
   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {