[llvm-commits] [llvm] r47457 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Author: lattner
Date: Thu Feb 21 14:54:31 2008
New Revision: 47457

URL: http://llvm.org/viewvc/llvm-project?rev=47457&view=rev
Log:
Make the clobber analysis a bit more smart: we only are careful about 
early clobbers if the clobber list contains a *register* not some thing
like {memory}, {dirflag} etc.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=47457&r1=47456&r2=47457&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 21 14:54:31 2008
@@ -3735,9 +3735,19 @@
     SawEarlyClobber |= OpInfo.isEarlyClobber;
     
     // If we see a clobber of a register, it is an early clobber.
-    if (OpInfo.Type == InlineAsm::isClobber &&
-        OpInfo.ConstraintType == TargetLowering::C_Register)
-      SawEarlyClobber = true;
+    if (!SawEarlyClobber &&
+        OpInfo.Type == InlineAsm::isClobber &&
+        OpInfo.ConstraintType == TargetLowering::C_Register) {
+      // Note that we want to ignore things that we don't trick here, like
+      // dirflag, fpsr, flags, etc.
+      std::pair<unsigned, const TargetRegisterClass*> PhysReg = 
+        TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
+                                         OpInfo.ConstraintVT);
+      if (PhysReg.first || PhysReg.second) {
+        // This is a register we know of.
+        SawEarlyClobber = true;
+      }
+    }
     
     // If this is a memory input, and if the operand is not indirect, do what we
     // need to to provide an address for the memory input.