[llvm-commits] [llvm] r44037 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/IA64/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/
Bill Wendling
isanbard at gmail.com
Mon Nov 12 16:44:26 PST 2007
Author: void
Date: Mon Nov 12 18:44:25 2007
New Revision: 44037
URL: http://llvm.org/viewvc/llvm-project?rev=44037&view=rev
Log:
Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).
This can only result in tears...
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.td
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Nov 12 18:44:25 2007
@@ -275,6 +275,20 @@
return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
}
+ /// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must have a
+ /// flag result (to ensure it's not CSE'd).
+ SDOperand getCALLSEQ_END(SDOperand Chain, SDOperand Op1, SDOperand Op2,
+ SDOperand InFlag) {
+ SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
+ SmallVector<SDOperand, 4> Ops;
+ Ops.push_back(Chain);
+ Ops.push_back(Op1);
+ Ops.push_back(Op2);
+ Ops.push_back(InFlag);
+ return getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0],
+ Ops.size() - (InFlag.Val == 0 ? 1 : 0));
+ }
+
/// getNode - Gets or creates the specified node.
///
SDOperand getNode(unsigned Opcode, MVT::ValueType VT);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 12 18:44:25 2007
@@ -1142,12 +1142,20 @@
// The only option for this is to custom lower it.
Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
assert(Tmp3.Val && "Target didn't custom lower this node!");
- assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
+
+ // The number of incoming and outgoing values should match; unless the final
+ // outgoing value is a flag.
+ assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
+ (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
+ Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
+ MVT::Flag)) &&
"Lowering call/formal_arguments produced unexpected # results!");
// Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
// remember that we legalized all of them, so it doesn't get relegalized.
for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
+ if (Tmp3.Val->getValueType(i) == MVT::Flag)
+ continue;
Tmp1 = LegalizeOp(Tmp3.getValue(i));
if (Op.ResNo == i)
Tmp2 = Tmp1;
@@ -1472,6 +1480,12 @@
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
" not tell us which reg is the stack pointer!");
SDOperand Chain = Tmp1.getOperand(0);
+
+ // Chain the dynamic stack allocation so that it doesn't modify the stack
+ // pointer when other instructions are using the stack.
+ Chain = DAG.getCALLSEQ_START(Chain,
+ DAG.getConstant(0, TLI.getPointerTy()));
+
SDOperand Size = Tmp2.getOperand(1);
SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
Chain = SP.getValue(1);
@@ -1482,7 +1496,14 @@
SP = DAG.getNode(ISD::AND, VT, SP,
DAG.getConstant(-(uint64_t)Align, VT));
Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
- Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
+ Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
+
+ Tmp2 =
+ DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(0, TLI.getPointerTy()),
+ DAG.getConstant(0, TLI.getPointerTy()),
+ SDOperand());
+
Tmp1 = LegalizeOp(Tmp1);
Tmp2 = LegalizeOp(Tmp2);
break;
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 12 18:44:25 2007
@@ -605,10 +605,10 @@
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
- SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
- Chain = DAG.getNode(ISD::CALLSEQ_END,
- DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
- ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, MVT::i32),
+ DAG.getConstant(0, MVT::i32),
+ InFlag);
if (RetVT != MVT::Other)
InFlag = Chain.getValue(1);
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 12 18:44:25 2007
@@ -17,7 +17,9 @@
//
// Type profiles.
-def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def SDT_ARMCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def SDT_ARMCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
@@ -45,10 +47,10 @@
def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
-def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
+def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq_start,
[SDNPHasChain, SDNPOutFlag]>;
-def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
- [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq_end,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
@@ -663,9 +665,9 @@
let Defs = [SP], Uses = [SP] in {
def ADJCALLSTACKUP :
-PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
- "@ ADJCALLSTACKUP $amt",
- [(ARMcallseq_end imm:$amt)]>;
+PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
+ "@ ADJCALLSTACKUP $amt1",
+ [(ARMcallseq_end imm:$amt1, imm:$amt2)]>;
def ADJCALLSTACKDOWN :
PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Nov 12 18:44:25 2007
@@ -162,9 +162,9 @@
let Defs = [SP], Uses = [SP] in {
def tADJCALLSTACKUP :
-PseudoInst<(outs), (ins i32imm:$amt),
- "@ tADJCALLSTACKUP $amt",
- [(ARMcallseq_end imm:$amt)]>, Requires<[IsThumb]>;
+PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+ "@ tADJCALLSTACKUP $amt1",
+ [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>;
def tADJCALLSTACKDOWN :
PseudoInst<(outs), (ins i32imm:$amt),
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Mon Nov 12 18:44:25 2007
@@ -769,10 +769,13 @@
bool isThumb = AFI->isThumbFunction();
ARMCC::CondCodes Pred = isThumb
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
- unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
+ // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
+ unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
emitSPUpdate(MBB, I, -Amount, Pred, PredReg, isThumb, TII);
} else {
+ // Note: PredReg is operand 3 for ADJCALLSTACKUP.
+ unsigned PredReg = isThumb ? 0 : Old->getOperand(3).getReg();
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
emitSPUpdate(MBB, I, Amount, Pred, PredReg, isThumb, TII);
}
Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Mon Nov 12 18:44:25 2007
@@ -374,8 +374,10 @@
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, getPointerTy()),
+ DAG.getConstant(0, getPointerTy()),
+ SDOperand());
SDOperand RetVal = TheCall;
if (RetTyVT != ActualRetTyVT) {
Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Mon Nov 12 18:44:25 2007
@@ -30,11 +30,14 @@
[SDNPHasChain, SDNPOptInFlag]>;
// These are target-independent nodes, but have target-specific formats.
-def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq,
+def SDT_AlphaCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
+def SDT_AlphaCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i64>,
+ SDTCisVT<1, i64> ]>;
+
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq_start,
[SDNPHasChain, SDNPOutFlag]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq,
- [SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq_end,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
//********************
//Paterns for matching
@@ -148,11 +151,14 @@
def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
-def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJUP $amt",
+def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
+ "; ADJUP $amt",
[(callseq_start imm:$amt)], s_pseudo>;
-def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJDOWN $amt",
- [(callseq_end imm:$amt)], s_pseudo>;
+def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt1, s64imm:$amt2),
+ "; ADJDOWN $amt1",
+ [(callseq_end imm:$amt1, imm:$amt2)], s_pseudo>;
}
+
def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
def PCLABEL : PseudoInstAlpha<(outs), (ins s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>;
def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
Modified: llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/IA64/IA64ISelLowering.cpp Mon Nov 12 18:44:25 2007
@@ -535,9 +535,10 @@
}
}
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(NumBytes, getPointerTy()));
-
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, getPointerTy()),
+ DAG.getConstant(0, getPointerTy()),
+ SDOperand());
return std::make_pair(RetVal, Chain);
}
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Nov 12 18:44:25 2007
@@ -399,12 +399,10 @@
}
// Create the CALLSEQ_END node.
- NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- Ops.clear();
- Ops.push_back(Chain);
- Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
- Ops.push_back(InFlag);
- Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, getPointerTy()),
+ DAG.getConstant(0, getPointerTy()),
+ InFlag);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Nov 12 18:44:25 2007
@@ -34,11 +34,14 @@
SDNPOptInFlag]>;
// These are target-independent nodes, but have target-specific formats.
-def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
- [SDNPHasChain, SDNPOutFlag]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
+def SDT_MipsCallSeq_start : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def SDT_MipsCallSeq_end : SDTypeProfile<0, 2, [SDTCisVT<0, i32>,
+ SDTCisVT<1, i32>]>;
+
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq_start,
[SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq_end,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
//===----------------------------------------------------------------------===//
// Mips Instruction Predicate Definitions.
@@ -348,9 +351,9 @@
def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt),
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
-def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt),
- "!ADJCALLSTACKUP $amt",
- [(callseq_end imm:$amt)]>;
+def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
+ "!ADJCALLSTACKUP $amt1",
+ [(callseq_end imm:$amt1, imm:$amt2)]>;
}
def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Nov 12 18:44:25 2007
@@ -1816,6 +1816,13 @@
Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
InFlag = Chain.getValue(1);
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, PtrVT),
+ DAG.getConstant(0, PtrVT),
+ InFlag);
+ if (Op.Val->getValueType(0) != MVT::Other)
+ InFlag = Chain.getValue(1);
+
SDOperand ResultVals[3];
unsigned NumResults = 0;
NodeTys.clear();
@@ -1878,8 +1885,6 @@
break;
}
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(NumBytes, PtrVT));
NodeTys.push_back(MVT::Other);
// If the function returns void, just return the chain.
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Nov 12 18:44:25 2007
@@ -23,8 +23,9 @@
def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
]>;
-def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
-
+def SDT_PPCCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def SDT_PPCCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
def SDT_PPCvperm : SDTypeProfile<1, 3, [
SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
]>;
@@ -90,10 +91,10 @@
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
// These are target-independent nodes, but have target-specific formats.
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
- [SDNPHasChain, SDNPOutFlag]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq_start,
[SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq_end,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
@@ -318,9 +319,9 @@
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
"${:comment} ADJCALLSTACKDOWN",
[(callseq_start imm:$amt)]>;
-def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
+def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
"${:comment} ADJCALLSTACKUP",
- [(callseq_end imm:$amt)]>;
+ [(callseq_end imm:$amt1, imm:$amt2)]>;
}
def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
Modified: llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Nov 12 18:44:25 2007
@@ -675,9 +675,10 @@
}
}
- Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
- DAG.getConstant(ArgsSize, getPointerTy()));
-
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(ArgsSize, getPointerTy()),
+ DAG.getConstant(0, getPointerTy()),
+ SDOperand());
return std::make_pair(RetVal, Chain);
}
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Mon Nov 12 18:44:25 2007
@@ -114,11 +114,14 @@
def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
// These are target-independent nodes, but have target-specific formats.
-def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq,
- [SDNPHasChain, SDNPOutFlag]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq,
+def SDT_SPCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def SDT_SPCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
+
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq_start,
[SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq_end,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def call : SDNode<"SPISD::CALL", SDT_SPCall,
@@ -205,9 +208,9 @@
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
-def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt),
- "!ADJCALLSTACKUP $amt",
- [(callseq_end imm:$amt)]>;
+def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+ "!ADJCALLSTACKUP $amt1",
+ [(callseq_end imm:$amt1, imm:$amt2)]>;
}
def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
"!IMPLICIT_DEF $dst",
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 12 18:44:25 2007
@@ -1131,14 +1131,12 @@
// This is common for Darwin/X86, Linux & Mingw32 targets.
NumBytesForCalleeToPush = isSRet ? 4 : 0;
}
-
- NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
- Ops.clear();
- Ops.push_back(Chain);
- Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
- Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
- Ops.push_back(InFlag);
- Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
+
+ Chain = DAG.getCALLSEQ_END(Chain,
+ DAG.getConstant(NumBytes, getPointerTy()),
+ DAG.getConstant(NumBytesForCalleeToPush,
+ getPointerTy()),
+ InFlag);
InFlag = Chain.getValue(1);
// Handle result values, copying them out of physregs into vregs that we
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=44037&r1=44036&r2=44037&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Nov 12 18:44:25 2007
@@ -253,7 +253,8 @@
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
// which can clobber EFLAGS.
let Defs = [ESP, EFLAGS], Uses = [ESP] in {
-def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN",
+def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
+ "#ADJCALLSTACKDOWN",
[(X86callseq_start imm:$amt)]>;
def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
"#ADJCALLSTACKUP",
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