[llvm-commits] [llvm] r43819 - /llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

[Evan Cheng]

Author: evancheng
Date: Wed Nov  7 02:08:25 2007
New Revision: 43819

URL: http://llvm.org/viewvc/llvm-project?rev=43819&view=rev
Log:
Simplify my (il)logic.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=43819&r1=43818&r2=43819&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Nov  7 02:08:25 2007
@@ -316,6 +316,7 @@
         if (!mop.isRegister())
           continue;
         unsigned Reg = mop.getReg();
+        unsigned RegI = Reg;
         if (Reg == 0 || MRegisterInfo::isPhysicalRegister(Reg))
           continue;
         bool isSubReg = RegMap->isSubRegister(Reg);
@@ -381,17 +382,7 @@
           unsigned RegJ = MI->getOperand(j).getReg();
           if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ))
             continue;
-          bool isSubRegJ = RegMap->isSubRegister(RegJ);
-          if (isSubRegJ) {
-            assert(!isSubReg || RegMap->getSubRegisterIndex(RegJ) == SubIdx);
-            RegJ = RegMap->getSuperRegister(RegJ);
-          }
-          // Important to check "isSubRegJ == isSubReg".
-          // e.g. %reg1024 = MOVSX32rr16 %reg1025. It's possible that both
-          // registers are coalesced to the same register but only %reg1025 is
-          // a sub-register use. They should not be rewritten to the same
-          // register.
-          if (RegJ == li.reg && isSubRegJ == isSubReg) {
+          if (RegJ == RegI) {
             MI->getOperand(j).setReg(NewVReg);
             HasUse |= MI->getOperand(j).isUse();
             HasDef |= MI->getOperand(j).isDef();