[llvm-commits] [llvm] r37892 - /llvm/trunk/lib/Target/Target.td

[Chris Lattner]

>>> +/// execute". If isOutput is true, then this is output operand.
>>
>> I don't get it.  What is an "output predicate"?  I see you use this
>> in the arm backend:
>>
>> +// Conditional code result for cmp, etc.
>> +//
>> +def cc_out : PredicateResultOperand<OtherVT, (ops CCR), (ops (i32
>> zero_reg))> {
>>     let PrintMethod = "printPredicateOperand";
>>   }
>>
>> why not just have cmp have an implicit def of the flags?  It seems
>> very very strange to me to have a "predicate" that is an output...
>
> Let's first  talk about why this is needed. For ARM, almost every
> instruction has a 's' bit. When the bit is set, the instruction will
> modify the CPSR register. So we'll model it as a PredicateOperand
> whose default value is zero_reg. This allows us to toggle the
> instruction by changing its register to CPSR (i.e. the 's' variant)
> without having a separate opcode.
>
> This is exactly the same mechanism as the input PredicateOperand.
> While I don't like the name PredicateOperand, I don't see the need to
> add something new.

For the record, Evan and I discussed this.  We finally decided that  
the only part I didn't like was the name, so he since renamed it to  
OptionalDefOperand.

This is a really cool facility that will let us elegantly describe  
the PPC "." instructions and other things as well.

-Chris