[llvm-commits] ARM problem

[Dan Gohman]

Hi Lauro,

This was caused by my fix for PR1529.

I'm currently considering the following patch, which fixes your attached
test case:

Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp,v
retrieving revision 1.470
diff -u -r1.470 SelectionDAGISel.cpp
--- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -312,7 +312,9 @@
     MVT::ValueType ElementVT;
     NumRegisters = TLI.getVectorTypeBreakdown(VT, ElementVT, RegisterVT);
   } else {
-    RegisterVT = TLI.getTypeToTransformTo(VT);
+    RegisterVT = VT;
+    while (!TLI.isTypeLegal(RegisterVT))
+      RegisterVT = TLI.getTypeToTransformTo(RegisterVT);
     NumRegisters = TLI.getNumRegisters(VT);
   }
 

I'm looking to see if I can find a cleaner way to solve this.

Dan

-- 
Dan Gohman, Cray Inc.