[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMISelLowering.cpp updated: 1.54 -> 1.55
---
Log message:

Silence some compilation warnings.

---
Diffs of the changes:  (+2 -2)

 ARMISelLowering.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.54 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.55
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.54	Thu May 17 19:19:34 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp	Thu May 17 20:19:57 2007
@@ -1369,7 +1369,7 @@
   unsigned SrcOff = 0, DstOff = 0;
   MVT::ValueType VT = MVT::i32;
   unsigned VTSize = 4;
-  const int MAX_LOADS_IN_LDM = 6;
+  const unsigned MAX_LOADS_IN_LDM = 6;
   SDOperand LoadChains[MAX_LOADS_IN_LDM];
   SDOperand Loads[MAX_LOADS_IN_LDM];
 
@@ -1377,7 +1377,7 @@
   // number of stores.  The loads and stores will get combined into
   // ldm/stm later on.
   while(EmittedNumMemOps < NumMemOps) {
-    unsigned int i;
+    unsigned i;
     for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) {
       Loads[i] = DAG.getLoad(VT, Chain,
                              DAG.getNode(ISD::ADD, VT, Src,