[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp
Evan Cheng
evan.cheng at apple.com
Thu May 17 17:19:52 PDT 2007
Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.53 -> 1.54
---
Log message:
Set ARM if-conversion block size threshold to 10 instructions for now.
---
Diffs of the changes: (+2 -2)
ARMISelLowering.cpp | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.53 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.54
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.53 Thu May 17 16:31:21 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp Thu May 17 19:19:34 2007
@@ -124,6 +124,7 @@
addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
}
+ computeRegisterProperties();
// ARM does not have f32 extending load.
setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
@@ -252,9 +253,8 @@
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
setStackPointerRegisterToSaveRestore(ARM::SP);
-
setSchedulingPreference(SchedulingForRegPressure);
- computeRegisterProperties();
+ setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
}
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