[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMRegisterInfo.cpp updated: 1.64 -> 1.65
---
Log message:

Rename.

---
Diffs of the changes:  (+7 -6)

 ARMRegisterInfo.cpp |   13 +++++++------
 1 files changed, 7 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.64 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.65
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.64	Wed Feb  7 15:19:58 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Wed Feb  7 15:24:09 2007
@@ -371,11 +371,12 @@
   BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx);
 }
 
-/// emitThumbRegPlusConstPool - Emits a series of instructions to materialize
-/// a destreg = basereg + immediate in Thumb code. Load the immediate from a
+/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
+/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
+/// in a register using mov / mvn sequences or load the immediate from a
 /// constpool entry.
 static
-void emitThumbRegPlusConstPool(MachineBasicBlock &MBB,
+void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator &MBBI,
                                unsigned DestReg, unsigned BaseReg,
                                int NumBytes, bool CanChangeCC,
@@ -471,7 +472,7 @@
   if (NumMIs > Threshold) {
     // This will expand into too many instructions. Load the immediate from a
     // constpool entry.
-    emitThumbRegPlusConstPool(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
+    emitThumbRegPlusImmInReg(MBB, MBBI, DestReg, BaseReg, NumBytes, true, TII);
     return;
   }
 
@@ -795,7 +796,7 @@
       bool UseRR = false;
       if (Opcode == ARM::tRestore) {
         if (FrameReg == ARM::SP)
-          emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,Offset,false,TII);
+          emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
         else {
           emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
           UseRR = true;
@@ -828,7 +829,7 @@
         BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12).addReg(ARM::R3);
       if (Opcode == ARM::tSpill) {
         if (FrameReg == ARM::SP)
-          emitThumbRegPlusConstPool(MBB, II, TmpReg, FrameReg,Offset,false,TII);
+          emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII);
         else {
           emitLoadConstPool(MBB, II, TmpReg, Offset, TII);
           UseRR = true;