[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMRegisterInfo.cpp updated: 1.63 -> 1.64
---
Log message:

If sp offset will be materialized in a register. Clear the offset field of str / ldr.

---
Diffs of the changes:  (+10 -8)

 ARMRegisterInfo.cpp |   18 ++++++++++--------
 1 files changed, 10 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.63 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.64
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.63	Wed Feb  7 15:18:32 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Wed Feb  7 15:19:58 2007
@@ -762,16 +762,18 @@
       return;
     }
 
+    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
+    if (AddrMode == ARMII::AddrModeTs) {
+      // Thumb tLDRspi, tSTRspi. These will change to instructions that use
+      // a different base register.
+      NumBits = 5;
+      Mask = (1 << NumBits) - 1;
+    }
     // If this is a thumb spill / restore, we will be using a constpool load to
     // materialize the offset.
-    bool isThumSpillRestore = Opcode == ARM::tRestore || Opcode == ARM::tSpill;
-    if (AddrMode == ARMII::AddrModeTs && !isThumSpillRestore) {
-      if (AddrMode == ARMII::AddrModeTs) {
-        // Thumb tLDRspi, tSTRspi. These will change to instructions that use
-        // a different base register.
-        NumBits = 5;
-        Mask = (1 << NumBits) - 1;
-      }
+    if (AddrMode == ARMII::AddrModeTs && isThumSpillRestore)
+      ImmOp.ChangeToImmediate(0);
+    else {
       // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
       ImmedOffset = ImmedOffset & Mask;
       if (isSub)