[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.8 -> 1.9
ARMRegisterInfo.cpp updated: 1.7 -> 1.8
---
Log message:

initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)


---
Diffs of the changes:  (+23 -1)

 ARMInstrInfo.td     |    4 +++-
 ARMRegisterInfo.cpp |   20 ++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.8 llvm/lib/Target/ARM/ARMInstrInfo.td:1.9
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.8	Sat Jul 15 20:02:57 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Jul 18 12:00:30 2006
@@ -53,7 +53,9 @@
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;
 
-def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+let isReturn = 1 in {
+  def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
+}
 
 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
 


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.7 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.8
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.7	Tue Jul 11 06:36:48 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Tue Jul 18 12:00:30 2006
@@ -116,10 +116,30 @@
 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 
 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
+  MachineBasicBlock &MBB = MF.front();
+  MachineFrameInfo  *MFI = MF.getFrameInfo();
+  int           NumBytes = (int) MFI->getStackSize();
+
+  //hack
+  assert(NumBytes == 0);
+
+  //add a sp = sp - 4
+  BuildMI(MBB, MBB.begin(), ARM::str, 1, ARM::R14).addReg(ARM::R13);
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
 				   MachineBasicBlock &MBB) const {
+  MachineBasicBlock::iterator MBBI = prior(MBB.end());
+  assert(MBBI->getOpcode() == ARM::bx &&
+         "Can only insert epilog into returning blocks");
+
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+  int          NumBytes = (int) MFI->getStackSize();
+  //hack
+  assert(NumBytes == 0);
+
+  BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R14).addImm(0).addReg(ARM::R13);
+  //add a sp = sp + 4
 }
 
 unsigned ARMRegisterInfo::getRARegister() const {