[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h

[Chris Lattner]

Changes in directory llvm/include/llvm/CodeGen:

ScheduleDAG.h updated: 1.20 -> 1.21
---
Log message:

Simplify the interface to the schedulers, to not pass the selected heuristic
in.


---
Diffs of the changes:  (+4 -14)

 ScheduleDAG.h |   18 ++++--------------
 1 files changed, 4 insertions(+), 14 deletions(-)


Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.20 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.21
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.20	Fri Mar 10 01:41:52 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h	Fri Mar 10 01:48:52 2006
@@ -34,16 +34,6 @@
   typedef std::vector<NodeInfoPtr>           NIVector;
   typedef std::vector<NodeInfoPtr>::iterator NIIterator;
 
-  // Scheduling heuristics
-  enum SchedHeuristics {
-    defaultScheduling,      // Let the target specify its preference.
-    noScheduling,           // No scheduling, emit breadth first sequence.
-    simpleScheduling,       // Two pass, min. critical path, max. utilization.
-    simpleNoItinScheduling, // Same as above exact using generic latency.
-    listSchedulingBURR,     // Bottom up reg reduction list scheduling.
-    listSchedulingTD        // Top-down list scheduler.
-  };
-  
   /// HazardRecognizer - This determines whether or not an instruction can be
   /// issued this cycle, and whether or not a noop needs to be inserted to handle
   /// the hazard.
@@ -296,8 +286,7 @@
                 const TargetMachine &tm)
       : DAG(dag), BB(bb), TM(tm) {}
 
-    virtual ~ScheduleDAG() {
-    };
+    virtual ~ScheduleDAG() {}
 
     /// Run - perform scheduling.
     ///
@@ -337,10 +326,11 @@
                     std::map<SDNode*, unsigned> &VRBaseMap);
   };
 
+  ScheduleDAG *createBFS_DAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB);
+  
   /// createSimpleDAGScheduler - This creates a simple two pass instruction
   /// scheduler.
-  ScheduleDAG* createSimpleDAGScheduler(SchedHeuristics Heuristic,
-                                        SelectionDAG &DAG,
+  ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG &DAG,
                                         MachineBasicBlock *BB);
 
   /// createBURRListDAGScheduler - This creates a bottom up register usage