[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h

[Chris Lattner]

Changes in directory llvm/include/llvm/CodeGen:

ScheduleDAG.h updated: 1.19 -> 1.20
---
Log message:

Move some simple-sched-specific instance vars to the simple scheduler.


---
Diffs of the changes:  (+2 -23)

 ScheduleDAG.h |   25 ++-----------------------
 1 files changed, 2 insertions(+), 23 deletions(-)


Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.19 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.20
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.19	Fri Mar 10 01:35:10 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h	Fri Mar 10 01:41:52 2006
@@ -284,7 +284,6 @@
 
   class ScheduleDAG {
   public:
-    SchedHeuristics Heuristic;            // Scheduling heuristic
     SelectionDAG &DAG;                    // DAG of the current basic block
     MachineBasicBlock *BB;                // Current basic block
     const TargetMachine &TM;              // Target processor
@@ -292,38 +291,18 @@
     const MRegisterInfo *MRI;             // Target processor register info
     SSARegMap *RegMap;                    // Virtual/real register map
     MachineConstantPool *ConstPool;       // Target constant pool
-    std::map<SDNode *, NodeInfo *> Map;   // Map nodes to info
-    unsigned NodeCount;                   // Number of nodes in DAG
-    bool HasGroups;                       // True if there are any groups
-    NodeInfo *Info;                       // Info for nodes being scheduled
-    NIVector Ordering;                    // Emit ordering of nodes
-    NodeGroup *HeadNG, *TailNG;           // Keep track of allocated NodeGroups
 
-    ScheduleDAG(SchedHeuristics hstc, SelectionDAG &dag, MachineBasicBlock *bb,
+    ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
                 const TargetMachine &tm)
-      : Heuristic(hstc), DAG(dag), BB(bb), TM(tm), NodeCount(0),
-        HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {}
+      : DAG(dag), BB(bb), TM(tm) {}
 
     virtual ~ScheduleDAG() {
-      if (Info)
-        delete[] Info;
-
-      NodeGroup *NG = HeadNG;
-      while (NG) {
-        NodeGroup *NextSU = NG->Next;
-        delete NG;
-        NG = NextSU;
-      }
     };
 
     /// Run - perform scheduling.
     ///
     MachineBasicBlock *Run();
 
-    /// getNI - Returns the node info for the specified node.
-    ///
-    NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
-  
     /// isPassiveNode - Return true if the node is a non-scheduled leaf.
     ///
     static bool isPassiveNode(SDNode *Node) {