[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.162 -> 1.163
---
Log message:

If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out. 

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.


---
Diffs of the changes:  (+9 -0)

 SelectionDAGISel.cpp |    9 +++++++++
 1 files changed, 9 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.162 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.163
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.162	Wed Feb 15 16:12:35 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Feb 16 02:27:55 2006
@@ -562,6 +562,15 @@
     } else {
       std::vector<SDOperand> Ops;
       Ops.push_back(getRoot());
+      // If the false case is the current basic block, then this is a self
+      // loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
+      // adds an extra instruction in the loop.  Instead, invert the
+      // condition and emit "Loop: ... br!cond Loop; br Out. 
+      if (CurMBB == Succ1MBB) {
+        std::swap(Succ0MBB, Succ1MBB);
+        SDOperand True = DAG.getConstant(1, Cond.getValueType());
+        Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
+      }
       Ops.push_back(Cond);
       Ops.push_back(DAG.getBasicBlock(Succ0MBB));
       Ops.push_back(DAG.getBasicBlock(Succ1MBB));