[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelPattern.cpp AlphaInstrInfo.td
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Wed Nov 30 09:11:32 PST 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.8 -> 1.9
AlphaISelLowering.cpp updated: 1.11 -> 1.12
AlphaISelPattern.cpp updated: 1.190 -> 1.191
AlphaInstrInfo.td updated: 1.75 -> 1.76
---
Log message:
Make typesafe that which isn't: FCMOVxx
---
Diffs of the changes: (+52 -26)
AlphaISelDAGToDAG.cpp | 12 +++++++++---
AlphaISelLowering.cpp | 3 +--
AlphaISelPattern.cpp | 32 +++++++++++++++++++++-----------
AlphaInstrInfo.td | 31 +++++++++++++++++++++----------
4 files changed, 52 insertions(+), 26 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.8 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.9
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.8 Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Nov 30 11:11:20 2005
@@ -335,6 +335,7 @@
unsigned Opc = Alpha::WTF;
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
bool rev = false;
+ bool isNE = false;
switch(CC) {
default: N->dump(); assert(0 && "Unknown FP comparison!");
case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
@@ -342,13 +343,17 @@
case ISD::SETLE: Opc = Alpha::CMPTLE; break;
case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
- //case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
+ case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
};
SDOperand tmp1 = Select(N->getOperand(0)),
tmp2 = Select(N->getOperand(1));
SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
rev?tmp2:tmp1,
rev?tmp1:tmp2);
+ if (isNE)
+ cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
+ CurDAG->getRegister(Alpha::F31, MVT::f64));
+
SDOperand LD;
if (AlphaLowering.hasITOF()) {
LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
@@ -372,6 +377,7 @@
case ISD::SELECT:
if (MVT::isFloatingPoint(N->getValueType(0))) {
//move int to fp
+ bool isDouble = N->getValueType(0) == MVT::f64;
SDOperand LD,
cond = Select(N->getOperand(0)),
TV = Select(N->getOperand(1)),
@@ -389,12 +395,12 @@
CurDAG->getRegister(Alpha::R31, MVT::i64),
ST);
}
- SDOperand FP = CurDAG->getTargetNode(Alpha::FCMOVEQ, MVT::f64, TV, FV, LD);
+ SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVEQT:Alpha::FCMOVEQS,
+ MVT::f64, TV, FV, LD);
return FP;
}
break;
-
}
return SelectCode(Op);
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.11 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.12
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.11 Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Nov 30 11:11:20 2005
@@ -98,8 +98,7 @@
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
- //Doesn't work yet
- setOperationAction(ISD::SETCC, MVT::f32, Promote);
+ setOperationAction(ISD::SETCC, MVT::f32, Promote);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.190 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.191
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.190 Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Wed Nov 30 11:11:20 2005
@@ -1317,7 +1317,7 @@
bool invTest = false;
unsigned Tmp3;
-
+ bool isD = CC.getOperand(0).getValueType() == MVT::f64;
ConstantFPSDNode *CN;
if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
@@ -1332,21 +1332,31 @@
{
unsigned Tmp1 = SelectExpr(CC.getOperand(0));
unsigned Tmp2 = SelectExpr(CC.getOperand(1));
- bool isD = CC.getOperand(0).getValueType() == MVT::f64;
Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
.addReg(Tmp1).addReg(Tmp2);
}
- switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
- default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
- case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
- case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
- case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
- case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
- case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
- case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
- }
+ if(isD)
+ switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
+ default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+ case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNET : Alpha::FCMOVEQT; break;
+ case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTT : Alpha::FCMOVLTT; break;
+ case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGET : Alpha::FCMOVLET; break;
+ case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTT : Alpha::FCMOVGTT; break;
+ case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLET : Alpha::FCMOVGET; break;
+ case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQT : Alpha::FCMOVNET; break;
+ }
+ else
+ switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
+ default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
+ case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNES : Alpha::FCMOVEQS; break;
+ case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGTS : Alpha::FCMOVLTS; break;
+ case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGES : Alpha::FCMOVLES; break;
+ case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLTS : Alpha::FCMOVGTS; break;
+ case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLES : Alpha::FCMOVGES; break;
+ case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQS : Alpha::FCMOVNES; break;
+ }
BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
return Result;
}
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.75 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.76
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.75 Wed Nov 30 10:10:29 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Nov 30 11:11:20 2005
@@ -162,16 +162,6 @@
def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
(CMOVEQ GPRC:$src1, GPRC:$src2, GPRC:$which)>;
-//conditional moves, fp
-let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
- isTwoAddress = 1 in {
-def FCMOVEQ : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
-def FCMOVGE : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
-def FCMOVGT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
-def FCMOVLE : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
-def FCMOVLT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
-def FCMOVNE : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
-}
def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
[(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))]>;
@@ -555,6 +545,27 @@
}
//TODO: Add lots more FP patterns
+//conditional moves, floats
+let OperandList = (ops F4RC:$RDEST, F4RC:$RSRC2, F4RC:$RSRC, F8RC:$RCOND),
+ isTwoAddress = 1 in {
+def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+}
+//conditional moves, doubles
+let OperandList = (ops F8RC:$RDEST, F8RC:$RSRC2, F8RC:$RSRC, F8RC:$RCOND),
+ isTwoAddress = 1 in {
+def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if = zero
+def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if >= zero
+def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if > zero
+def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if <= zero
+def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RSRC,$RDEST",[]>; // FCMOVE if < zero
+def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RSRC,$RDEST",[]>; //FCMOVE if != zero
+}
+
let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
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