[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h AlphaISelPattern.cpp AlphaInstrInfo.td
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Wed Nov 30 08:10:48 PST 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.7 -> 1.8
AlphaISelLowering.cpp updated: 1.10 -> 1.11
AlphaISelLowering.h updated: 1.4 -> 1.5
AlphaISelPattern.cpp updated: 1.189 -> 1.190
AlphaInstrInfo.td updated: 1.74 -> 1.75
---
Log message:
FPSelect and more custom lowering
---
Diffs of the changes: (+69 -25)
AlphaISelDAGToDAG.cpp | 29 ++++++++++++++++++++++++++++-
AlphaISelLowering.cpp | 27 +++++++++++++++++++++++++--
AlphaISelLowering.h | 2 +-
AlphaISelPattern.cpp | 28 ++++++++--------------------
AlphaInstrInfo.td | 8 +++++++-
5 files changed, 69 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.7 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.8
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.7 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Nov 30 10:10:29 2005
@@ -368,8 +368,35 @@
return FP;
}
break;
+
+ case ISD::SELECT:
+ if (MVT::isFloatingPoint(N->getValueType(0))) {
+ //move int to fp
+ SDOperand LD,
+ cond = Select(N->getOperand(0)),
+ TV = Select(N->getOperand(1)),
+ FV = Select(N->getOperand(2));
+
+ if (AlphaLowering.hasITOF()) {
+ LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
+ } else {
+ int FrameIdx =
+ CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+ SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
+ SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
+ cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
+ LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
+ CurDAG->getRegister(Alpha::R31, MVT::i64),
+ ST);
+ }
+ SDOperand FP = CurDAG->getTargetNode(Alpha::FCMOVEQ, MVT::f64, TV, FV, LD);
+ return FP;
+ }
+ break;
+
+
}
-
+
return SelectCode(Op);
}
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.10 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.11
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.10 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Nov 30 10:10:29 2005
@@ -73,7 +73,9 @@
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
-
+ setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
+
if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
@@ -412,7 +414,28 @@
isDouble?MVT::f64:MVT::f32, LD);
return FP;
}
+ case ISD::FP_TO_SINT: {
+ bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
+ SDOperand src = Op.getOperand(0);
+
+ if (!isDouble) //Promote
+ src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
+
+ src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
+
+ if (useITOF) {
+ return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
+ } else {
+ int FrameIdx =
+ DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
+ SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
+ SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+ src, FI, DAG.getSrcValue(0));
+ return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
+ }
+ }
+
}
+
return SDOperand();
}
-
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.4 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.5
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.4 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Wed Nov 30 10:10:29 2005
@@ -26,7 +26,7 @@
// Start the numbering where the builting ops and target ops leave off.
FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END,
//These corrospond to the identical Instruction
- ITOFT_, FTOIT_, CVTQT_, CVTQS_,
+ ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_,
};
}
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.189 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.190
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.189 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Wed Nov 30 10:10:29 2005
@@ -1297,26 +1297,6 @@
return Result;
}
- case ISD::FP_TO_UINT:
- case ISD::FP_TO_SINT:
- {
- assert (DestType == MVT::i64 && "only quads can be loaded to");
- MVT::ValueType SrcType = N.getOperand(0).getValueType();
- assert (SrcType == MVT::f32 || SrcType == MVT::f64);
- Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
- if (SrcType == MVT::f32)
- {
- Tmp2 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
- Tmp1 = Tmp2;
- }
- Tmp2 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
- MoveFP2Int(Tmp2, Result, true);
-
- return Result;
- }
-
case ISD::SELECT:
if (isFP) {
//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
@@ -1567,10 +1547,18 @@
BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0)));
return Result;
+ case AlphaISD::CVTTQ_:
+ BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+ return Result;
+
case AlphaISD::ITOFT_:
BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
return Result;
+ case AlphaISD::FTOIT_:
+ BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0)));
+ return Result;
+
case ISD::AssertSext:
case ISD::AssertZext:
return SelectExpr(N.getOperand(0));
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.74 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.75
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.74 Wed Nov 30 01:19:56 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Nov 30 10:10:29 2005
@@ -24,6 +24,7 @@
def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
+def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_", SDTFPUnaryOp, []>;
//********************
@@ -575,7 +576,8 @@
def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
[(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))]>;
let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
-def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",[]>; //Convert T_floating to quadword
+def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",
+ [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))]>;
let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in
def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
[(set F8RC:$RC, (fextend F4RC:$RB))]>;
@@ -686,3 +688,7 @@
(CPYSNT F8RC:$RB, F8RC:$RB)>;
def : Pat<(fneg F4RC:$RB),
(CPYSNS F4RC:$RB, F4RC:$RB)>;
+//Yes, signed multiply high is ugly
+def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
+ (SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA),
+ (CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;
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