[llvm-commits] CVS: llvm/lib/Target/TargetSelectionDAG.td

[Duraid Madina]

Changes in directory llvm/lib/Target:

TargetSelectionDAG.td updated: 1.7 -> 1.8
---
Log message:

add support for int->FP and FP->int ops, and add ia64 patterns for these 



---
Diffs of the changes:  (+11 -0)

 TargetSelectionDAG.td |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.7 llvm/lib/Target/TargetSelectionDAG.td:1.8
--- llvm/lib/Target/TargetSelectionDAG.td:1.7	Wed Oct 26 12:00:25 2005
+++ llvm/lib/Target/TargetSelectionDAG.td	Mon Oct 31 21:07:25 2005
@@ -94,6 +94,12 @@
 def SDTFPExtendOp  : SDTypeProfile<1, 1, [   // fextend
   SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
 ]>;
+def SDTIntToFPOp : SDTypeProfile<1, 1, [   // [su]int_to_fp 
+  SDTCisFP<0>, SDTCisInt<1>
+]>;
+def SDTFPToIntOp : SDTypeProfile<1, 1, [   // fp_to_[su]int 
+  SDTCisInt<0>, SDTCisFP<1>
+]>;
 def SDTExtInreg : SDTypeProfile<1, 2, [   // sext_inreg
   SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
   SDTCisVTSmallerThanOp<2, 1>
@@ -172,6 +178,11 @@
 def fround     : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
 def fextend    : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
 
+def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
+def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
+def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
+def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
+
 def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
 
 //===----------------------------------------------------------------------===//