[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.30 -> 1.31
---
Log message:

Add assertions to the trivial scheduler to check that the value types match
up between defs and uses.


---
Diffs of the changes:  (+21 -0)

 ScheduleDAG.cpp |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.30 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.31
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.30	Sun Oct  2 01:34:16 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Oct  2 02:10:55 2005
@@ -1102,6 +1102,20 @@
         
         unsigned VReg = EmitDAG(Op.getOperand(i));
         MI->addRegOperand(VReg, MachineOperand::Use);
+        
+        // Verify that it is right.
+        assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+        assert(II.OpInfo[i+NumResults].RegClass &&
+               "Don't have operand info for this instruction!");
+#ifndef NDEBUG
+        if (RegMap->getRegClass(VReg) != II.OpInfo[i+NumResults].RegClass) {
+          std::cerr << "OP:  ";
+          Op.getOperand(i).Val->dump(&DAG); std::cerr << "\nUSE: ";
+          Op.Val->dump(&DAG); std::cerr << "\n";
+        }
+#endif
+        assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
+               "Register class of operand and regclass of use don't agree!");
       } else if (ConstantSDNode *C =
                                    dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
         MI->addZeroExtImm64Operand(C->getValue());
@@ -1129,6 +1143,13 @@
                "Chain and flag operands should occur at end of operand list!");
         unsigned VReg = EmitDAG(Op.getOperand(i));
         MI->addRegOperand(VReg, MachineOperand::Use);
+        
+        // Verify that it is right.
+        assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
+        assert(II.OpInfo[i+NumResults].RegClass &&
+               "Don't have operand info for this instruction!");
+        assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
+               "Register class of operand and regclass of use don't agree!");
       }
     }