[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.29 -> 1.30
---
Log message:

Codegen CopyFromReg using the regclass that matches the valuetype of the 
destination vreg.



---
Diffs of the changes:  (+11 -9)

 ScheduleDAG.cpp |   20 +++++++++++---------
 1 files changed, 11 insertions(+), 9 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.29 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.30
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.29	Sat Oct  1 02:45:09 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Oct  2 01:34:16 2005
@@ -1031,11 +1031,11 @@
       if (MRegisterInfo::isVirtualRegister(SrcReg)) {
         TRC = RegMap->getRegClass(SrcReg);
       } else {
-        // FIXME: we don't know what register class to generate this for.  Do
-        // a brute force search and pick the first match. :(
+        // Pick the register class of the right type that contains this physreg.
         for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
-               E = MRI.regclass_end(); I != E; ++I)
-          if ((*I)->contains(SrcReg)) {
+             E = MRI.regclass_end(); I != E; ++I)
+          if ((*I)->getType() == Node->getValueType(0) &&
+              (*I)->contains(SrcReg)) {
             TRC = *I;
             break;
           }
@@ -1100,7 +1100,8 @@
                Op.getOperand(i).getValueType() != MVT::Flag &&
                "Chain and flag operands should occur at end of operand list!");
         
-        MI->addRegOperand(EmitDAG(Op.getOperand(i)), MachineOperand::Use);
+        unsigned VReg = EmitDAG(Op.getOperand(i));
+        MI->addRegOperand(VReg, MachineOperand::Use);
       } else if (ConstantSDNode *C =
                                    dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
         MI->addZeroExtImm64Operand(C->getValue());
@@ -1126,7 +1127,8 @@
         assert(Op.getOperand(i).getValueType() != MVT::Other &&
                Op.getOperand(i).getValueType() != MVT::Flag &&
                "Chain and flag operands should occur at end of operand list!");
-        MI->addRegOperand(EmitDAG(Op.getOperand(i)), MachineOperand::Use);
+        unsigned VReg = EmitDAG(Op.getOperand(i));
+        MI->addRegOperand(VReg, MachineOperand::Use);
       }
     }
 
@@ -1188,11 +1190,11 @@
       if (MRegisterInfo::isVirtualRegister(SrcReg)) {
         TRC = RegMap->getRegClass(SrcReg);
       } else {
-        // FIXME: we don't know what register class to generate this for.  Do
-        // a brute force search and pick the first match. :(
+        // Pick the register class of the right type that contains this physreg.
         for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
                E = MRI.regclass_end(); I != E; ++I)
-          if ((*I)->contains(SrcReg)) {
+          if ((*I)->getType() == Op.Val->getValueType(0) &&
+              (*I)->contains(SrcReg)) {
             TRC = *I;
             break;
           }