[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp PPC32ISelDAGToDAG.cpp PPC32ISelLowering.cpp PPC32ISelPattern.cpp
Chris Lattner
lattner at cs.uiuc.edu
Fri Sep 30 18:35:23 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32CodeEmitter.cpp updated: 1.34 -> 1.35
PPC32ISelDAGToDAG.cpp updated: 1.88 -> 1.89
PPC32ISelLowering.cpp updated: 1.27 -> 1.28
PPC32ISelPattern.cpp updated: 1.180 -> 1.181
---
Log message:
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
---
Diffs of the changes: (+113 -44)
PPC32CodeEmitter.cpp | 3 +-
PPC32ISelDAGToDAG.cpp | 73 ++++++++++++++++++++++++++++++++++++++------------
PPC32ISelLowering.cpp | 13 ++++++--
PPC32ISelPattern.cpp | 68 +++++++++++++++++++++++++++++++---------------
4 files changed, 113 insertions(+), 44 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.34 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.35
--- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.34 Wed Aug 24 18:08:16 2005
+++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp Fri Sep 30 20:35:02 2005
@@ -125,7 +125,8 @@
emitWord(getBinaryCodeForInstr(*I));
break;
case PPC::IMPLICIT_DEF_GPR:
- case PPC::IMPLICIT_DEF_FP:
+ case PPC::IMPLICIT_DEF_F8:
+ case PPC::IMPLICIT_DEF_F4:
break; // pseudo opcode, no side effects
case PPC::MovePCtoLR:
assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.88 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.89
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.88 Fri Sep 30 18:43:37 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp Fri Sep 30 20:35:02 2005
@@ -443,8 +443,10 @@
LHS, getI32Imm(Lo16(Imm)));
return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
LHS, Select(RHS));
+ } else if (LHS.getValueType() == MVT::f32) {
+ return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
} else {
- return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
+ return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
}
}
@@ -679,8 +681,10 @@
case ISD::UNDEF:
if (N->getValueType(0) == MVT::i32)
CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
- else
- CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
+ else if (N->getValueType(0) == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
+ else
+ CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
return SDOperand(N, 0);
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
@@ -749,10 +753,16 @@
return SDOperand(Result.Val, Op.ResNo);
}
case PPCISD::FSEL:
- CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
- Select(N->getOperand(0)),
- Select(N->getOperand(1)),
- Select(N->getOperand(2)));
+ if (N->getValueType(0) == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32,
+ Select(N->getOperand(0)),
+ Select(N->getOperand(1)),
+ Select(N->getOperand(2)));
+ else
+ CurDAG->SelectNodeTo(N, PPC::FSELD, MVT::f64,
+ Select(N->getOperand(0)),
+ Select(N->getOperand(1)),
+ Select(N->getOperand(2)));
return SDOperand(N, 0);
case PPCISD::FCFID:
CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
@@ -956,15 +966,17 @@
return SDOperand(N, 0);
}
case ISD::FABS:
- CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
- Select(N->getOperand(0)));
+ if (N->getValueType(0) == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::FABSS, MVT::f32, Select(N->getOperand(0)));
+ else
+ CurDAG->SelectNodeTo(N, PPC::FABSD, MVT::f64, Select(N->getOperand(0)));
return SDOperand(N, 0);
case ISD::FP_EXTEND:
assert(MVT::f64 == N->getValueType(0) &&
MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
// We need to emit an FMR to make sure that the result has the right value
// type.
- CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0)));
+ CurDAG->SelectNodeTo(N, PPC::FMRSD, MVT::f64, Select(N->getOperand(0)));
return SDOperand(N, 0);
case ISD::FP_ROUND:
assert(MVT::f32 == N->getValueType(0) &&
@@ -978,7 +990,8 @@
unsigned Opc;
switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
default: Opc = 0; break;
- case PPC::FABS: Opc = PPC::FNABS; break;
+ case PPC::FABSS: Opc = PPC::FNABSS; break;
+ case PPC::FABSD: Opc = PPC::FNABSD; break;
case PPC::FMADD: Opc = PPC::FNMADD; break;
case PPC::FMADDS: Opc = PPC::FNMADDS; break;
case PPC::FMSUB: Opc = PPC::FNMSUB; break;
@@ -988,7 +1001,7 @@
// inverted opcode and the original instruction's operands. Otherwise,
// fall through and generate a fneg instruction.
if (Opc) {
- if (PPC::FNABS == Opc)
+ if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
else
CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
@@ -996,7 +1009,10 @@
return SDOperand(N, 0);
}
}
- CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
+ if (Ty == MVT::f32)
+ CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
+ else
+ CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f64, Val);
return SDOperand(N, 0);
}
case ISD::FSQRT: {
@@ -1090,9 +1106,26 @@
case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
}
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
- Op1, Op2, Select(N->getOperand(0)));
- return SDOperand(N, Op.ResNo);
+ // If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
+ // copy'.
+ if (TypeBeingLoaded != MVT::f32 || N->getOpcode() == ISD::LOAD) {
+ CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
+ Op1, Op2, Select(N->getOperand(0)));
+ return SDOperand(N, Op.ResNo);
+ } else {
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Op1);
+ Ops.push_back(Op2);
+ Ops.push_back(Select(N->getOperand(0)));
+ SDOperand Res = CurDAG->getTargetNode(Opc, MVT::f32, MVT::Other, Ops);
+ SDOperand Ext = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Res);
+ CodeGenMap[Op.getValue(0)] = Ext;
+ CodeGenMap[Op.getValue(1)] = Res.getValue(1);
+ if (Op.ResNo)
+ return Res.getValue(1);
+ else
+ return Ext;
+ }
}
case ISD::TRUNCSTORE:
@@ -1250,7 +1283,13 @@
unsigned BROpc = getBCCForSetCC(CC);
bool isFP = MVT::isFloatingPoint(N->getValueType(0));
- unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int;
+ unsigned SelectCCOp;
+ if (MVT::isInteger(N->getValueType(0)))
+ SelectCCOp = PPC::SELECT_CC_Int;
+ else if (N->getValueType(0) == MVT::f32)
+ SelectCCOp = PPC::SELECT_CC_F4;
+ else
+ SelectCCOp = PPC::SELECT_CC_F8;
CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
Select(N->getOperand(2)), Select(N->getOperand(3)),
getI32Imm(BROpc));
Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.27 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.28
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.27 Wed Sep 28 17:29:58 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp Fri Sep 30 20:35:02 2005
@@ -33,8 +33,8 @@
// Set up the register classes.
addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
- addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
- addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
+ addRegisterClass(MVT::f32, PPC32::F4RCRegisterClass);
+ addRegisterClass(MVT::f64, PPC32::F8RCRegisterClass);
// PowerPC has no intrinsics for these particular operations
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
@@ -396,7 +396,11 @@
ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
if (!ArgLive) break;
if (FPR_remaining > 0) {
- unsigned VReg = RegMap->createVirtualRegister(&PPC32::FPRCRegClass);
+ unsigned VReg;
+ if (ObjectVT == MVT::f32)
+ VReg = RegMap->createVirtualRegister(&PPC32::F4RCRegClass);
+ else
+ VReg = RegMap->createVirtualRegister(&PPC32::F8RCRegClass);
MF.addLiveIn(FPR[FPR_idx], VReg);
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
--FPR_remaining;
@@ -724,7 +728,8 @@
PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
- MI->getOpcode() == PPC::SELECT_CC_FP) &&
+ MI->getOpcode() == PPC::SELECT_CC_F4 ||
+ MI->getOpcode() == PPC::SELECT_CC_F8) &&
"Unexpected instr type to insert");
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.180 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.181
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.180 Thu Sep 29 12:38:52 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Fri Sep 30 20:35:02 2005
@@ -87,9 +87,6 @@
inline unsigned MakeIntReg() {
return RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
}
- inline unsigned MakeFPReg() {
- return RegMap->createVirtualRegister(PPC32::FPRCRegisterClass);
- }
// dag -> dag expanders for integer divide by constant
SDOperand BuildSDIVSequence(SDOperand N);
@@ -593,8 +590,6 @@
unsigned ISel::SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC) {
unsigned Result, Tmp1, Tmp2;
bool AlreadySelected = false;
- static const unsigned CompareOpcodes[] =
- { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
// Allocate a condition register for this expression
Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
@@ -626,8 +621,13 @@
else
BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
} else {
- bool IsInteger = MVT::isInteger(LHS.getValueType());
- unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
+ unsigned CompareOpc;
+ if (MVT::isInteger(LHS.getValueType()))
+ CompareOpc = U ? PPC::CMPLW : PPC::CMPW;
+ else if (LHS.getValueType() == MVT::f32)
+ CompareOpc = PPC::FCMPUS;
+ else
+ CompareOpc = PPC::FCMPUD;
Tmp1 = SelectExpr(LHS);
Tmp2 = SelectExpr(RHS);
BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
@@ -815,7 +815,10 @@
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2));
- BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ if (N.getOperand(0).getValueType() == MVT::f32)
+ BuildMI(BB, PPC::FSELS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ else
+ BuildMI(BB, PPC::FSELD, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result;
case PPCISD::FCFID:
Tmp1 = SelectExpr(N.getOperand(0));
@@ -832,8 +835,10 @@
case ISD::UNDEF:
if (Node->getValueType(0) == MVT::i32)
BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Result);
+ else if (Node->getValueType(0) == MVT::f32)
+ BuildMI(BB, PPC::IMPLICIT_DEF_F4, 0, Result);
else
- BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Result);
+ BuildMI(BB, PPC::IMPLICIT_DEF_F8, 0, Result);
return Result;
case ISD::DYNAMIC_STACKALLOC:
// Generate both result values. FIXME: Need a better commment here?
@@ -1011,7 +1016,8 @@
case MVT::f64:
case MVT::f32:
assert(FPR_idx < 13 && "Too many fp args");
- BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgVR[i]);
+ BuildMI(BB, N.getOperand(i+2).getValueType() == MVT::f32 ? PPC::FMRS :
+ PPC::FMRD, 1, FPR[FPR_idx]).addReg(ArgVR[i]);
CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
++FPR_idx;
break;
@@ -1033,14 +1039,15 @@
}
break;
case MVT::f32:
+ BuildMI(BB, PPC::FMRS, 1, Result).addReg(PPC::F1);
+ break;
case MVT::f64:
- BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
+ BuildMI(BB, PPC::FMRD, 1, Result).addReg(PPC::F1);
break;
}
return Result+N.ResNo;
}
- case ISD::SIGN_EXTEND:
case ISD::SIGN_EXTEND_INREG:
Tmp1 = SelectExpr(N.getOperand(0));
switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
@@ -1063,8 +1070,10 @@
Tmp1 = dyn_cast<RegisterSDNode>(Node->getOperand(1))->getReg();
if (MVT::isInteger(DestType))
BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
+ else if (DestType == MVT::f32)
+ BuildMI(BB, PPC::FMRS, 1, Result).addReg(Tmp1);
else
- BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::FMRD, 1, Result).addReg(Tmp1);
return Result;
case ISD::SHL:
@@ -1655,16 +1664,26 @@
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
} else if (ISD::FABS == N.getOperand(0).getOpcode()) {
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
+ if (N.getOperand(0).getValueType() == MVT::f32)
+ BuildMI(BB, PPC::FNABSS, 1, Result).addReg(Tmp1);
+ else
+ BuildMI(BB, PPC::FNABSD, 1, Result).addReg(Tmp1);
+
} else {
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
+ if (N.getOperand(0).getValueType() == MVT::f32)
+ BuildMI(BB, PPC::FNEGS, 1, Result).addReg(Tmp1);
+ else
+ BuildMI(BB, PPC::FNEGD, 1, Result).addReg(Tmp1);
}
return Result;
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
+ if (N.getOperand(0).getValueType() == MVT::f32)
+ BuildMI(BB, PPC::FABSS, 1, Result).addReg(Tmp1);
+ else
+ BuildMI(BB, PPC::FABSD, 1, Result).addReg(Tmp1);
return Result;
case ISD::FSQRT:
@@ -1686,7 +1705,7 @@
N.getOperand(0).getValueType() == MVT::f32 &&
"only f32 to f64 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
+ BuildMI(BB, PPC::FMRSD, 1, Result).addReg(Tmp1);
return Result;
}
return 0;
@@ -1735,9 +1754,10 @@
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (Tmp1 != Tmp2) {
- if (N.getOperand(2).getValueType() == MVT::f64 ||
- N.getOperand(2).getValueType() == MVT::f32)
- BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
+ if (N.getOperand(2).getValueType() == MVT::f64)
+ BuildMI(BB, PPC::FMRD, 1, Tmp2).addReg(Tmp1);
+ else if (N.getOperand(2).getValueType() == MVT::f32)
+ BuildMI(BB, PPC::FMRS, 1, Tmp2).addReg(Tmp1);
else
BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
}
@@ -1747,8 +1767,10 @@
Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
if (N.getOperand(1).getValueType() == MVT::i32)
BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
+ else if (N.getOperand(1).getValueType() == MVT::f32)
+ BuildMI(BB, PPC::IMPLICIT_DEF_F4, 0, Tmp1);
else
- BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Tmp1);
+ BuildMI(BB, PPC::IMPLICIT_DEF_F8, 0, Tmp1);
return;
case ISD::RET:
switch (N.getNumOperands()) {
@@ -1771,8 +1793,10 @@
default:
assert(0 && "Unknown return type!");
case MVT::f64:
+ BuildMI(BB, PPC::FMRD, 1, PPC::F1).addReg(Tmp1);
+ break;
case MVT::f32:
- BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
+ BuildMI(BB, PPC::FMRS, 1, PPC::F1).addReg(Tmp1);
break;
case MVT::i32:
BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
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