[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td PowerPCBranchSelector.cpp PPC32RegisterInfo.td PPC32RegisterInfo.cpp PPC32InstrInfo.cpp
Chris Lattner
lattner at cs.uiuc.edu
Fri Sep 30 18:34:30 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PowerPCInstrInfo.td updated: 1.114 -> 1.115
PowerPCBranchSelector.cpp updated: 1.14 -> 1.15
PPC32RegisterInfo.td updated: 1.7 -> 1.8
PPC32RegisterInfo.cpp updated: 1.27 -> 1.28
PPC32InstrInfo.cpp updated: 1.5 -> 1.6
---
Log message:
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
---
Diffs of the changes: (+140 -108)
PPC32InstrInfo.cpp | 2
PPC32RegisterInfo.cpp | 82 +++++++++++-------------
PPC32RegisterInfo.td | 6 +
PowerPCBranchSelector.cpp | 3
PowerPCInstrInfo.td | 155 +++++++++++++++++++++++++++-------------------
5 files changed, 140 insertions(+), 108 deletions(-)
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.114 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.115
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.114 Thu Sep 29 18:34:24 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Fri Sep 30 20:34:18 2005
@@ -317,14 +317,17 @@
def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
}
def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
-def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
- def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
+ def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
+ i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
+ def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
}
@@ -463,15 +466,15 @@
def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
"cmpldi $dst, $src1, $src2">, isPPC64;
let isLoad = 1 in {
-def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
+def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
"lfs $rD, $disp($rA)">;
-def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
+def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
"lfd $rD, $disp($rA)">;
}
let isStore = 1 in {
-def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
+def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
"stfs $rS, $disp($rA)">;
-def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
+def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
"stfd $rS, $disp($rA)">;
}
@@ -596,51 +599,74 @@
"cmplw $crD, $rA, $rB">;
def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
"cmpld $crD, $rA, $rB">, isPPC64;
-def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
- "fcmpo $crD, $fA, $fB">;
-def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
+//def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
+// "fcmpo $crD, $fA, $fB">;
+def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
+ "fcmpu $crD, $fA, $fB">;
+def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
"fcmpu $crD, $fA, $fB">;
+
let isLoad = 1 in {
-def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
"lfsx $dst, $base, $index">;
-def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
"lfdx $dst, $base, $index">;
}
-def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
+def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
"fcfid $frD, $frB",
[]>, isPPC64;
-def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
+def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
"fctidz $frD, $frB",
[]>, isPPC64;
-def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
+def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
"fctiwz $frD, $frB",
[]>;
-def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
- "fabs $frD, $frB",
- [(set FPRC:$frD, (fabs FPRC:$frB))]>;
-def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
- "fmr $frD, $frB",
- []>; // (set FPRC:$frD, FPRC:$frB)
-def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
- "fnabs $frD, $frB",
- [(set FPRC:$frD, (fneg (fabs FPRC:$frB)))]>;
-def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
- "fneg $frD, $frB",
- [(set FPRC:$frD, (fneg FPRC:$frB))]>;
-def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
+def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
"frsp $frD, $frB",
[]>;
-def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
+def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
"fsqrt $frD, $frB",
- [(set FPRC:$frD, (fsqrt FPRC:$frB))]>;
-def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
+ [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
+def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
"fsqrts $frD, $frB",
[]>;
+
+/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
+def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
+ "fmr $frD, $frB",
+ []>; // (set F4RC:$frD, F4RC:$frB)
+def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
+ "fmr $frD, $frB",
+ []>; // (set F8RC:$frD, F8RC:$frB)
+def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
+ "fmr $frD, $frB",
+ []>; // (set F8RC:$frD, (fpextend F4RC:$frB))
+
+// These are artificially split into two different forms, for 4/8 byte FP.
+def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
+ "fabs $frD, $frB",
+ [(set F4RC:$frD, (fabs F4RC:$frB))]>;
+def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
+ "fabs $frD, $frB",
+ [(set F8RC:$frD, (fabs F8RC:$frB))]>;
+def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
+ "fnabs $frD, $frB",
+ [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
+def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
+ "fnabs $frD, $frB",
+ [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
+def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
+ "fneg $frD, $frB",
+ [(set F4RC:$frD, (fneg F4RC:$frB))]>;
+def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
+ "fneg $frD, $frB",
+ [(set F8RC:$frD, (fneg F8RC:$frB))]>;
+
let isStore = 1 in {
-def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
+def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
"stfsx $frS, $rA, $rB">;
-def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
+def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
"stfdx $frS, $rA, $rB">;
}
@@ -730,75 +756,80 @@
// this type.
//
def FMADD : AForm_1<63, 29,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fmadd $FRT, $FRA, $FRC, $FRB",
- [(set FPRC:$FRT, (fadd (fmul FPRC:$FRA, FPRC:$FRC),
- FPRC:$FRB))]>;
+ [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB))]>;
def FMADDS : AForm_1<59, 29,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fmadds $FRT, $FRA, $FRC, $FRB",
[]>;
def FMSUB : AForm_1<63, 28,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fmsub $FRT, $FRA, $FRC, $FRB",
- [(set FPRC:$FRT, (fsub (fmul FPRC:$FRA, FPRC:$FRC),
- FPRC:$FRB))]>;
+ [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB))]>;
def FMSUBS : AForm_1<59, 28,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fmsubs $FRT, $FRA, $FRC, $FRB",
[]>;
def FNMADD : AForm_1<63, 31,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fnmadd $FRT, $FRA, $FRC, $FRB",
- [(set FPRC:$FRT, (fneg (fadd (fmul FPRC:$FRA, FPRC:$FRC),
- FPRC:$FRB)))]>;
+ [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB)))]>;
def FNMADDS : AForm_1<59, 31,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fnmadds $FRT, $FRA, $FRC, $FRB",
[]>;
def FNMSUB : AForm_1<63, 30,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fnmsub $FRT, $FRA, $FRC, $FRB",
- [(set FPRC:$FRT, (fneg (fsub (fmul FPRC:$FRA, FPRC:$FRC),
- FPRC:$FRB)))]>;
+ [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
+ F8RC:$FRB)))]>;
def FNMSUBS : AForm_1<59, 30,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fnmsubs $FRT, $FRA, $FRC, $FRB",
[]>;
-def FSEL : AForm_1<63, 23,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
+// FSEL is artificially split into 4 and 8-byte forms.
+def FSELD : AForm_1<63, 23,
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+ "fsel $FRT, $FRA, $FRC, $FRB",
+ []>;
+def FSELS : AForm_1<63, 23,
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FADD : AForm_2<63, 21,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fadd $FRT, $FRA, $FRB",
- [(set FPRC:$FRT, (fadd FPRC:$FRA, FPRC:$FRB))]>;
+ [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
def FADDS : AForm_2<59, 21,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
"fadds $FRT, $FRA, $FRB",
[]>;
def FDIV : AForm_2<63, 18,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fdiv $FRT, $FRA, $FRB",
- [(set FPRC:$FRT, (fdiv FPRC:$FRA, FPRC:$FRB))]>;
+ [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
def FDIVS : AForm_2<59, 18,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
"fdivs $FRT, $FRA, $FRB",
[]>;
def FMUL : AForm_3<63, 25,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fmul $FRT, $FRA, $FRB",
- [(set FPRC:$FRT, (fmul FPRC:$FRA, FPRC:$FRB))]>;
+ [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
def FMULS : AForm_3<59, 25,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
"fmuls $FRT, $FRA, $FRB",
[]>;
def FSUB : AForm_2<63, 20,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fsub $FRT, $FRA, $FRB",
- [(set FPRC:$FRT, (fsub FPRC:$FRA, FPRC:$FRB))]>;
+ [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
def FSUBS : AForm_2<59, 20,
- (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
+ (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
"fsubs $FRT, $FRA, $FRB",
[]>;
Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.14 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.15
--- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.14 Fri Aug 26 18:41:27 2005
+++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp Fri Sep 30 20:34:18 2005
@@ -41,7 +41,8 @@
// keeping the offsets up to date later when we emit long branch glue.
return 12;
case PPC::IMPLICIT_DEF_GPR: // no asm emitted
- case PPC::IMPLICIT_DEF_FP: // no asm emitted
+ case PPC::IMPLICIT_DEF_F4: // no asm emitted
+ case PPC::IMPLICIT_DEF_F8: // no asm emitted
return 0;
default:
break;
Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.7 llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.8
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.td:1.7 Fri Aug 19 14:13:20 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.td Fri Sep 30 20:34:18 2005
@@ -39,8 +39,12 @@
}];
}
-def FPRC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
+def F8RC : RegisterClass<"PPC32", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+def F4RC : RegisterClass<"PPC32", f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7,
+ F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
+ F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
+
def CRRC : RegisterClass<"PPC32", i32, 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>;
Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.27 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.28
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.27 Fri Sep 30 16:28:27 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Fri Sep 30 20:34:18 2005
@@ -43,47 +43,26 @@
ImmToIdxMap[PPC::ADDI] = PPC::ADD;
}
-static unsigned getIdx(const TargetRegisterClass *RC) {
- if (RC == PPC32::GPRCRegisterClass) {
- switch (RC->getSize()) {
- default: assert(0 && "Invalid data size!");
- case 1: return 0;
- case 2: return 1;
- case 4: return 2;
- }
- } else if (RC == PPC32::FPRCRegisterClass) {
- switch (RC->getSize()) {
- default: assert(0 && "Invalid data size!");
- case 4: return 3;
- case 8: return 4;
- }
- } else if (RC == PPC32::CRRCRegisterClass) {
- switch (RC->getSize()) {
- default: assert(0 && "Invalid data size!");
- case 4: return 2;
- }
- }
- std::cerr << "Invalid register class to getIdx()!\n";
- abort();
-}
-
void
PPC32RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
- static const unsigned Opcode[] = {
- PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
- };
- unsigned OC = Opcode[getIdx(RC)];
if (SrcReg == PPC::LR) {
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
- addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
} else if (RC == PPC32::CRRCRegisterClass) {
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
- addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
+ } else if (RC == PPC32::GPRCRegisterClass) {
+ addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
+ } else if (RC == PPC32::F8RCRegisterClass) {
+ addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
+ } else if (RC == PPC32::F4RCRegisterClass) {
+ addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
} else {
- addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
+ assert(0 && "Unknown regclass!");
+ abort();
}
}
@@ -92,18 +71,21 @@
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
- static const unsigned Opcode[] = {
- PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
- };
- unsigned OC = Opcode[getIdx(RC)];
if (DestReg == PPC::LR) {
- addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC32::CRRCRegisterClass) {
- addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
+ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
+ } else if (RC == PPC32::GPRCRegisterClass) {
+ addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
+ } else if (RC == PPC32::F8RCRegisterClass) {
+ addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
+ } else if (RC == PPC32::F4RCRegisterClass) {
+ addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
} else {
- addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
+ assert(0 && "Unknown regclass!");
+ abort();
}
}
@@ -115,8 +97,10 @@
if (RC == PPC32::GPRCRegisterClass) {
BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (RC == PPC32::FPRCRegisterClass) {
- BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
+ } else if (RC == PPC32::F4RCRegisterClass) {
+ BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
+ } else if (RC == PPC32::F8RCRegisterClass) {
+ BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
} else if (RC == PPC32::CRRCRegisterClass) {
BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
} else {
@@ -130,6 +114,9 @@
switch (MI->getOpcode()) {
default: break;
case PPC::LWZ:
+ //
+ // case PPC::LFS: // ENABLE!!
+ //
case PPC::LFD:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
MI->getOperand(2).isFrameIndex()) {
@@ -161,8 +148,7 @@
return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
}
- } else if (Opc == PPC::FMR) {
- // We currently always spill FP values as doubles. :(
+ } else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
return addFrameReference(BuildMI(PPC::STFD,
@@ -171,6 +157,15 @@
unsigned OutReg = MI->getOperand(0).getReg();
return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex);
}
+ } else if (Opc == PPC::FMRS) {
+ if (OpNum == 0) { // move -> store
+ unsigned InReg = MI->getOperand(1).getReg();
+ return addFrameReference(BuildMI(PPC::STFS,
+ 3).addReg(InReg), FrameIndex);
+ } else { // move -> load
+ unsigned OutReg = MI->getOperand(0).getReg();
+ return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex);
+ }
}
return 0;
}
@@ -262,7 +257,8 @@
MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
MI.SetMachineOperandReg(2, PPC::R0);
} else {
- MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
+ MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
+ Offset);
}
}
Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.5 llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.6
--- llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.5 Fri Sep 9 13:17:41 2005
+++ llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp Fri Sep 30 20:34:18 2005
@@ -57,7 +57,7 @@
destReg = MI.getOperand(0).getReg();
return true;
}
- } else if (oc == PPC::FMR) { // fmr r1, r2
+ } else if (oc == PPC::FMRS || oc == PPC::FMRD) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
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