[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp PPC32ISelLowering.cpp PPC32ISelPattern.cpp
Chris Lattner
lattner at cs.uiuc.edu
Wed Sep 28 15:30:10 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelDAGToDAG.cpp updated: 1.81 -> 1.82
PPC32ISelLowering.cpp updated: 1.26 -> 1.27
PPC32ISelPattern.cpp updated: 1.178 -> 1.179
---
Log message:
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
---
Diffs of the changes: (+120 -114)
PPC32ISelDAGToDAG.cpp | 74 ++++++++++++-------------
PPC32ISelLowering.cpp | 12 ++--
PPC32ISelPattern.cpp | 148 ++++++++++++++++++++++++++------------------------
3 files changed, 120 insertions(+), 114 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.81 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.82
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.81 Wed Sep 28 13:12:37 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp Wed Sep 28 17:29:58 2005
@@ -767,22 +767,20 @@
CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
Select(N->getOperand(0)));
return SDOperand(N, 0);
- case ISD::ADD: {
- MVT::ValueType Ty = N->getValueType(0);
- if (Ty == MVT::i32) {
- if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
- PPC::ADDIS, PPC::ADDI, true)) {
- CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
- N = I;
- } else {
- CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
- Select(N->getOperand(1)));
- }
- return SDOperand(N, 0);
+ case ISD::ADD:
+ if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
+ PPC::ADDIS, PPC::ADDI, true)) {
+ CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
+ N = I;
+ } else {
+ CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
+ Select(N->getOperand(1)));
}
-
+ return SDOperand(N, 0);
+ case ISD::FADD: {
+ MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
- if (N->getOperand(0).getOpcode() == ISD::MUL &&
+ if (N->getOperand(0).getOpcode() == ISD::FMUL &&
N->getOperand(0).Val->hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
@@ -790,7 +788,7 @@
Select(N->getOperand(0).getOperand(1)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
- } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
+ } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
N->getOperand(1).hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
@@ -806,30 +804,30 @@
return SDOperand(N, 0);
}
case ISD::SUB: {
- MVT::ValueType Ty = N->getValueType(0);
- if (Ty == MVT::i32) {
- unsigned Imm;
- if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
- if (0 == Imm)
- CurDAG->SelectNodeTo(N, PPC::NEG, Ty, Select(N->getOperand(1)));
- else
- CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)),
- getI32Imm(Lo16(Imm)));
- return SDOperand(N, 0);
- }
- if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
- PPC::ADDIS, PPC::ADDI, true, true)) {
- CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
- N = I;
- } else {
- CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)),
- Select(N->getOperand(0)));
- }
+ unsigned Imm;
+ if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
+ if (0 == Imm)
+ CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, Select(N->getOperand(1)));
+ else
+ CurDAG->SelectNodeTo(N, PPC::SUBFIC, MVT::i32, Select(N->getOperand(1)),
+ getI32Imm(Lo16(Imm)));
return SDOperand(N, 0);
}
+ if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
+ PPC::ADDIS, PPC::ADDI, true, true)) {
+ CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
+ N = I;
+ } else {
+ CurDAG->SelectNodeTo(N, PPC::SUBF, MVT::i32, Select(N->getOperand(1)),
+ Select(N->getOperand(0)));
+ }
+ return SDOperand(N, 0);
+ }
+ case ISD::FSUB: {
+ MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
- if (N->getOperand(0).getOpcode() == ISD::MUL &&
+ if (N->getOperand(0).getOpcode() == ISD::FMUL &&
N->getOperand(0).Val->hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
@@ -837,7 +835,7 @@
Select(N->getOperand(0).getOperand(1)),
Select(N->getOperand(1)));
return SDOperand(N, 0);
- } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
+ } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
N->getOperand(1).Val->hasOneUse()) {
++FusedFP; // Statistic
CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
@@ -852,6 +850,7 @@
Select(N->getOperand(1)));
return SDOperand(N, 0);
}
+ case ISD::FMUL:
case ISD::MUL: {
unsigned Imm, Opc;
if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
@@ -869,7 +868,8 @@
Select(N->getOperand(1)));
return SDOperand(N, 0);
}
- case ISD::SDIV: {
+ case ISD::SDIV:
+ case ISD::FDIV: {
unsigned Imm;
if (isIntImmediate(N->getOperand(1), Imm)) {
if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.26 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.27
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.26 Tue Sep 27 17:18:25 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp Wed Sep 28 17:29:58 2005
@@ -52,10 +52,10 @@
// We don't support sin/cos/sqrt/fmod
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
- setOperationAction(ISD::SREM , MVT::f64, Expand);
+ setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
- setOperationAction(ISD::SREM , MVT::f32, Expand);
+ setOperationAction(ISD::FREM , MVT::f32, Expand);
// If we're enabling GP optimizations, use hardware square root
if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
@@ -208,19 +208,19 @@
case ISD::SETULT:
case ISD::SETLT:
return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
+ DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS), FV, TV);
case ISD::SETUGE:
case ISD::SETGE:
return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
+ DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS), TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
+ DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS), FV, TV);
case ISD::SETULE:
case ISD::SETLE:
return DAG.getNode(PPCISD::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
+ DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS), TV, FV);
}
break;
}
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.178 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.179
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.178 Fri Sep 9 19:21:05 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Wed Sep 28 17:29:58 2005
@@ -1133,40 +1133,40 @@
return Result;
case ISD::ADD:
- if (!MVT::isInteger(DestType)) {
- if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
- N.getOperand(0).Val->hasOneUse()) {
- ++FusedFP; // Statistic
- Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
- Tmp3 = SelectExpr(N.getOperand(1));
- Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
- BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- return Result;
- }
- if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
- N.getOperand(1).Val->hasOneUse()) {
- ++FusedFP; // Statistic
- Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
- Tmp3 = SelectExpr(N.getOperand(0));
- Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
- BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- return Result;
- }
- Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
- Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
- return Result;
- }
if (SelectIntImmediateExpr(N, Result, PPC::ADDIS, PPC::ADDI, true))
return Result;
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
-
+
+ case ISD::FADD:
+ if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::FMUL &&
+ N.getOperand(0).Val->hasOneUse()) {
+ ++FusedFP; // Statistic
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
+ Tmp3 = SelectExpr(N.getOperand(1));
+ Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
+ BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ return Result;
+ }
+ if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::FMUL &&
+ N.getOperand(1).Val->hasOneUse()) {
+ ++FusedFP; // Statistic
+ Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
+ Tmp3 = SelectExpr(N.getOperand(0));
+ Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
+ BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ return Result;
+ }
+ Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
+
case ISD::AND:
if (isIntImmediate(N.getOperand(1), Tmp2)) {
if (isShiftedMask_32(Tmp2) || isShiftedMask_32(~Tmp2)) {
@@ -1290,34 +1290,33 @@
return Result;
}
- case ISD::SUB:
- if (!MVT::isInteger(DestType)) {
- if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
- N.getOperand(0).Val->hasOneUse()) {
- ++FusedFP; // Statistic
- Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
- Tmp3 = SelectExpr(N.getOperand(1));
- Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
- BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- return Result;
- }
- if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
- N.getOperand(1).Val->hasOneUse()) {
- ++FusedFP; // Statistic
- Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
- Tmp3 = SelectExpr(N.getOperand(0));
- Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
- BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
- return Result;
- }
- Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
- Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ case ISD::FSUB:
+ if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::FMUL &&
+ N.getOperand(0).Val->hasOneUse()) {
+ ++FusedFP; // Statistic
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
+ Tmp3 = SelectExpr(N.getOperand(1));
+ Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
+ BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result;
}
+ if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::FMUL &&
+ N.getOperand(1).Val->hasOneUse()) {
+ ++FusedFP; // Statistic
+ Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
+ Tmp3 = SelectExpr(N.getOperand(0));
+ Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
+ BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+ return Result;
+ }
+ Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
+ case ISD::SUB:
if (isIntImmediate(N.getOperand(0), Tmp1) && isInt16(Tmp1)) {
Tmp1 = Lo16(Tmp1);
Tmp2 = SelectExpr(N.getOperand(1));
@@ -1334,6 +1333,13 @@
BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
return Result;
+ case ISD::FMUL:
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, DestType == MVT::f32 ? PPC::FMULS : PPC::FMUL, 2,
+ Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
+
case ISD::MUL:
Tmp1 = SelectExpr(N.getOperand(0));
if (isIntImmediate(N.getOperand(1), Tmp2) && isInt16(Tmp2)) {
@@ -1341,13 +1347,7 @@
BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
} else {
Tmp2 = SelectExpr(N.getOperand(1));
- switch (DestType) {
- default: assert(0 && "Unknown type to ISD::MUL"); break;
- case MVT::i32: Opc = PPC::MULLW; break;
- case MVT::f32: Opc = PPC::FMULS; break;
- case MVT::f64: Opc = PPC::FMUL; break;
- }
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
@@ -1359,6 +1359,17 @@
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
+ case ISD::FDIV:
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ switch (DestType) {
+ default: assert(0 && "Unknown type to ISD::FDIV"); break;
+ case MVT::f32: Opc = PPC::FDIVS; break;
+ case MVT::f64: Opc = PPC::FDIV; break;
+ }
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
+
case ISD::SDIV:
if (isIntImmediate(N.getOperand(1), Tmp3)) {
if ((signed)Tmp3 > 0 && isPowerOf2_32(Tmp3)) {
@@ -1392,12 +1403,7 @@
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
- switch (DestType) {
- default: assert(0 && "Unknown type to ISD::DIV"); break;
- case MVT::i32: Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW; break;
- case MVT::f32: Opc = PPC::FDIVS; break;
- case MVT::f64: Opc = PPC::FDIV; break;
- }
+ Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW; break;
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
@@ -1624,9 +1630,9 @@
case ISD::FNEG:
if (!NoExcessFPPrecision &&
- ISD::ADD == N.getOperand(0).getOpcode() &&
+ ISD::FADD == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
- ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
+ ISD::FMUL == N.getOperand(0).getOperand(0).getOpcode() &&
N.getOperand(0).getOperand(0).Val->hasOneUse()) {
++FusedFP; // Statistic
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
@@ -1635,9 +1641,9 @@
Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
} else if (!NoExcessFPPrecision &&
- ISD::ADD == N.getOperand(0).getOpcode() &&
+ ISD::FADD == N.getOperand(0).getOpcode() &&
N.getOperand(0).Val->hasOneUse() &&
- ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
+ ISD::FMUL == N.getOperand(0).getOperand(1).getOpcode() &&
N.getOperand(0).getOperand(1).Val->hasOneUse()) {
++FusedFP; // Statistic
Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
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