[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.4 -> 1.5
AlphaISelPattern.cpp updated: 1.170 -> 1.171
---
Log message:

Add FP versions of the binary operators, keeping the int and fp worlds seperate.
Though I have done extensive testing, it is possible that this will break
things in configs I can't test.  Please let me know if this causes a problem
and I'll fix it ASAP.


---
Diffs of the changes:  (+22 -33)

 AlphaISelLowering.cpp |    4 +--
 AlphaISelPattern.cpp  |   51 +++++++++++++++++++-------------------------------
 2 files changed, 22 insertions(+), 33 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.4 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.5
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.4	Tue Sep 13 14:03:13 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Wed Sep 28 17:29:17 2005
@@ -68,8 +68,8 @@
   setOperationAction(ISD::SEXTLOAD, MVT::i8,  Expand);
   setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
   
-  setOperationAction(ISD::SREM, MVT::f32, Expand);
-  setOperationAction(ISD::SREM, MVT::f64, Expand);
+  setOperationAction(ISD::FREM, MVT::f32, Expand);
+  setOperationAction(ISD::FREM, MVT::f64, Expand);
   
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
   


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.170 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.171
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.170	Tue Sep 13 14:31:44 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Sep 28 17:29:17 2005
@@ -1275,10 +1275,7 @@
       case ISD::SHL: Opc = Alpha::SL; break;
       case ISD::SRL: Opc = Alpha::SRL; break;
       case ISD::SRA: Opc = Alpha::SRA; break;
-      case ISD::MUL:
-        Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS)
-          : Alpha::MULQ;
-        break;
+      case ISD::MUL: Opc = Alpha::MULQ; break;
       };
       Tmp1 = SelectExpr(N.getOperand(0));
       Tmp2 = SelectExpr(N.getOperand(1));
@@ -1288,25 +1285,7 @@
 
   case ISD::ADD:
   case ISD::SUB:
-    if (isFP) {
-      ConstantFPSDNode *CN;
-      if (opcode == ISD::ADD)
-        Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
-      else
-        Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
-      if (opcode == ISD::SUB
-          && (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
-          && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
-      {
-        Tmp2 = SelectExpr(N.getOperand(1));
-        BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
-      } else {
-        Tmp1 = SelectExpr(N.getOperand(0));
-        Tmp2 = SelectExpr(N.getOperand(1));
-        BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
-      }
-      return Result;
-    } else {
+    {
       bool isAdd = opcode == ISD::ADD;
 
       //first check for Scaled Adds and Subs!
@@ -1369,15 +1348,25 @@
       }
       return Result;
     }
-
+  case ISD::FADD:
+  case ISD::FSUB:
+  case ISD::FMUL:
+  case ISD::FDIV: {
+    if (opcode == ISD::FADD)
+      Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
+    else if (opcode == ISD::FSUB)
+      Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
+    else if (opcode == ISD::FMUL)
+      Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS;
+    else
+      Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
+    Tmp1 = SelectExpr(N.getOperand(0));
+    Tmp2 = SelectExpr(N.getOperand(1));
+    BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+    return Result;
+  }
   case ISD::SDIV:
-    if (isFP) {
-      Tmp1 = SelectExpr(N.getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(1));
-      BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result)
-        .addReg(Tmp1).addReg(Tmp2);
-      return Result;
-    } else {
+    {
       //check if we can convert into a shift!
       if (isSIntImmediate(N.getOperand(1), SImm) &&
           SImm != 0 && isPowerOf2_64(llabs(SImm))) {