[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelLowering.cpp updated: 1.13 -> 1.14
---
Log message:

Enable generation of AssertSext and AssertZext in the PPC backend.


---
Diffs of the changes:  (+7 -2)

 PPC32ISelLowering.cpp |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.13 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.14
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.13	Mon Aug 29 19:45:18 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp	Tue Aug 30 20:58:39 2005
@@ -214,8 +214,13 @@
         MF.addLiveIn(GPR[GPR_idx]);
         argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
                                             GPR[GPR_idx], MVT::i32);
-        if (ObjectVT != MVT::i32)
-          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
+        if (ObjectVT != MVT::i32) {
+          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
+                                                       : ISD::AssertZext;
+          argt = DAG.getNode(AssertOp, MVT::i32, argt, 
+                             DAG.getValueType(ObjectVT));
+          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
+        }
       } else {
         needsLoad = true;
       }