[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Nate Begeman]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.177 -> 1.178
---
Log message:

Remove some unnecessary casts, and add the AssertZext case to
MaskedValueIsZero.


---
Diffs of the changes:  (+3 -2)

 SelectionDAG.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.177 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.178
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.177	Tue Aug 30 17:38:38 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 30 19:27:53 2005
@@ -1095,6 +1095,7 @@
     SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
     return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
   case ISD::ZERO_EXTEND:
+  case ISD::AssertZext:
     SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
     return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
 
@@ -1228,8 +1229,8 @@
       case ISD::AND  : return getConstant(C1 & C2, VT);
       case ISD::OR   : return getConstant(C1 | C2, VT);
       case ISD::XOR  : return getConstant(C1 ^ C2, VT);
-      case ISD::SHL  : return getConstant(C1 << (int)C2, VT);
-      case ISD::SRL  : return getConstant(C1 >> (unsigned)C2, VT);
+      case ISD::SHL  : return getConstant(C1 << C2, VT);
+      case ISD::SRL  : return getConstant(C1 >> C2, VT);
       case ISD::SRA  : return getConstant(N1C->getSignExtended() >>(int)C2, VT);
       default: break;
       }