[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.176 -> 1.177
---
Log message:

Allow physregs to occur in the dag with multiple types.  Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point.  :(

This fixes compilation of mesa




---
Diffs of the changes:  (+8 -12)

 SelectionDAG.cpp |   20 ++++++++------------
 1 files changed, 8 insertions(+), 12 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.176 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.177
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.176	Mon Aug 29 21:54:28 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 30 17:38:38 2005
@@ -307,7 +307,8 @@
     ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0;
     break;
   case ISD::Register:
-    RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0;
+    RegNodes.erase(std::make_pair(cast<RegisterSDNode>(N)->getReg(),
+                                  N->getValueType(0)));
     break;
   case ISD::SRCVALUE: {
     SrcValueSDNode *SVN = cast<SrcValueSDNode>(N);
@@ -533,18 +534,13 @@
   return SDOperand(CondCodeNodes[Cond], 0);
 }
 
-SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) {
-  if (Reg >= RegNodes.size())
-    RegNodes.resize(Reg+1);
-  RegisterSDNode *&Result = RegNodes[Reg];
-  if (Result) {
-    assert(Result->getValueType(0) == VT &&
-           "Inconsistent value types for machine registers");
-  } else {
-    Result = new RegisterSDNode(Reg, VT);
-    AllNodes.push_back(Result);
+SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) {
+  RegisterSDNode *&Reg = RegNodes[std::make_pair(RegNo, VT)];
+  if (!Reg) {
+    Reg = new RegisterSDNode(RegNo, VT);
+    AllNodes.push_back(Reg);
   }
-  return SDOperand(Result, 0);
+  return SDOperand(Reg, 0);
 }
 
 SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,