[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.2 -> 1.3
---
Log message:

Be fruitful and multiply!


---
Diffs of the changes:  (+29 -0)

 PPC32ISelDAGToDAG.cpp |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.2 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.3
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.2	Wed Aug 17 18:46:35 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 17 19:21:41 2005
@@ -281,6 +281,35 @@
                          Select(N->getOperand(1)));
     break;
   }
+  case ISD::MUL: {
+    unsigned Imm, Opc;
+    if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
+      CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI, 
+                           Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
+      break;
+    } 
+    switch (N->getValueType(0)) {
+      default: assert(0 && "Unhandled multiply type!");
+      case MVT::i32: Opc = PPC::MULLW; break;
+      case MVT::f32: Opc = PPC::FMULS; break;
+      case MVT::f64: Opc = PPC::FMUL;  break;
+    }
+    CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)), 
+                         Select(N->getOperand(1)));
+    break;
+  }
+  case ISD::MULHS: {
+    assert(N->getValueType(0) == MVT::i32);
+    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHW, 
+                         Select(N->getOperand(0)), Select(N->getOperand(1)));
+    break;
+  }
+  case ISD::MULHU: {
+    assert(N->getValueType(0) == MVT::i32);
+    CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULHWU, 
+                         Select(N->getOperand(0)), Select(N->getOperand(1)));
+    break;
+  }
   case ISD::FNEG: {
     SDOperand Val = Select(N->getOperand(0));
     MVT::ValueType Ty = N->getValueType(0);