[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
Nate Begeman
natebegeman at mac.com
Wed Aug 17 16:46:48 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelDAGToDAG.cpp updated: 1.1 -> 1.2
---
Log message:
Teach the DAG->DAG ISel about FNEG, and how it can be used to invert
several of the PowerPC opcodes that come in both negated and non-negated
forms.
---
Diffs of the changes: (+29 -2)
PPC32ISelDAGToDAG.cpp | 31 +++++++++++++++++++++++++++++--
1 files changed, 29 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.1 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.2
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.1 Wed Aug 17 14:33:03 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp Wed Aug 17 18:46:35 2005
@@ -199,7 +199,6 @@
break;
}
}
-
case ISD::ADD: {
MVT::ValueType Ty = N->getValueType(0);
if (Ty == MVT::i32) {
@@ -281,7 +280,35 @@
Select(N->getOperand(0)),
Select(N->getOperand(1)));
break;
- }
+ }
+ case ISD::FNEG: {
+ SDOperand Val = Select(N->getOperand(0));
+ MVT::ValueType Ty = N->getValueType(0);
+ if (Val.Val->hasOneUse()) {
+ unsigned Opc;
+ switch (Val.getTargetOpcode()) {
+ default: Opc = 0; break;
+ case PPC::FABS: Opc = PPC::FNABS; break;
+ case PPC::FMADD: Opc = PPC::FNMADD; break;
+ case PPC::FMADDS: Opc = PPC::FNMADDS; break;
+ case PPC::FMSUB: Opc = PPC::FNMSUB; break;
+ case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
+ }
+ // If we inverted the opcode, then emit the new instruction with the
+ // inverted opcode and the original instruction's operands. Otherwise,
+ // fall through and generate a fneg instruction.
+ if (Opc) {
+ if (PPC::FNABS == Opc)
+ CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
+ else
+ CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
+ Val.getOperand(1), Val.getOperand(2));
+ break;
+ }
+ }
+ CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
+ break;
+ }
case ISD::RET: {
SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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