[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp

[Jim Laskey]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.135 -> 1.136
---
Log message:


1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
   (~x)|y and x|(~y) yielding ORC.


---
Diffs of the changes:  (+24 -3)

 PPC32ISelPattern.cpp |   27 ++++++++++++++++++++++++---
 1 files changed, 24 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.135 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.136
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.135	Thu Aug 11 16:59:22 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Fri Aug 12 18:38:02 2005
@@ -1717,10 +1717,17 @@
        return Result;
       }
     }
+    if (isOprNot(N.getOperand(1))) {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
+      BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      RecordSuccess = false;
+      return Result;
+    }
     if (isOprNot(N.getOperand(0))) {
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(1));
-      BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp2).addReg(Tmp1);
+      Tmp1 = SelectExpr(N.getOperand(1));
+      Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
+      BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2);
       RecordSuccess = false;
       return Result;
     }
@@ -1737,6 +1744,20 @@
       return Result;
     if (SelectIntImmediateExpr(N, Result, PPC::ORIS, PPC::ORI))
       return Result;
+    if (isOprNot(N.getOperand(1))) {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
+      BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      RecordSuccess = false;
+      return Result;
+    }
+    if (isOprNot(N.getOperand(0))) {
+      Tmp1 = SelectExpr(N.getOperand(1));
+      Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
+      BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2);
+      RecordSuccess = false;
+      return Result;
+    }
     // emit regular or
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));