[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
Jim Laskey
jlaskey at apple.com
Thu Aug 11 16:00:22 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelPattern.cpp updated: 1.134 -> 1.135
---
Log message:
1. Added the function isOpcWithIntImmediate to simplify testing of
operand with
specified opcode and an integer constant right operand.
2. Modified ISD::SHL, ISD::SRL, ISD::SRA to use rlwinm when applied
after a mask.
Test Cases
==========
int %test6(int %a) {
entry:
%tmp.1 = and int %a, 65280 ; <int> [#uses=1]
%tmp.2 = shr int %tmp.1, ubyte 8 ; <uint> [#uses=1]
ret int %tmp.2
}
uint %test7(uint %a) {
entry:
%tmp.1 = and uint %a, 65280 ; <uint> [#uses=1]
%tmp.2 = shr uint %tmp.1, ubyte 8 ; <uint> [#uses=1]
ret uint %tmp.2
}
int %test8(int %a) {
entry:
%tmp.1 = and int %a, 16711680 ; <int> [#uses=1]
%tmp.2 = shl int %tmp.1, ubyte 8 ; <int> [#uses=1]
ret int %tmp.2
}
Old Result
==========
.text
.align 2
.globl _test6
_test6:
.LBB_test6_0: ; entry
rlwinm r2, r3, 0, 16, 23
srawi r3, r2, 8
blr
.text
.align 2
.globl _test7
_test7:
.LBB_test7_0: ; entry
rlwinm r2, r3, 0, 16, 23
srwi r3, r2, 8
blr
.text
.align 2
.globl _test8
_test8:
.LBB_test8_0: ; entry
rlwinm r2, r3, 0, 8, 15
slwi r3, r2, 8
blr
New Result
==========
.text
.align 2
.globl _test6
_test6:
.LBB_test6_0: ; entry
rlwinm r3, r3, 24, 24, 31
blr
.text
.align 2
.globl _test7
_test7:
.LBB_test7_0: ; entry
rlwinm r3, r3, 24, 24, 31
blr
.text
.align 2
.globl _test8
_test8:
.LBB_test8_0: ; entry
rlwinm r3, r3, 8, 0, 7
blr
---
Diffs of the changes: (+40 -9)
PPC32ISelPattern.cpp
1 files changed, 40 insertions(+), 9 deletions(-)
Index: lib/Target/PowerPC/PPC32ISelPattern.cpp
===================================================================
RCS file: /var/cvs/llvm/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp,v
retrieving revision 1.134
diff -u -d -b -w -r1.134 PPC32ISelPattern.cpp
--- lib/Target/PowerPC/PPC32ISelPattern.cpp 11 Aug 2005 17:56:50
-0000 1.134
+++ lib/Target/PowerPC/PPC32ISelPattern.cpp 11 Aug 2005 21:48:56
-0000
@@ -664,6 +664,13 @@
return false;
}
+// isOpcWithIntImmediate - This method tests to see if the node is a
specific
+// opcode and that it has a immediate integer right operand.
+// If so Imm will receive the 32 bit value.
+static bool isOpcWithIntImmediate(SDOperand N, unsigned Opc,
unsigned& Imm) {
+ return N.getOpcode() == Opc && isIntImmediate(N.getOperand(1), Imm);
+}
+
// isOprShiftImm - Returns true if the specified operand is a shift
opcode with
// a immediate shift count less than 32.
static bool isOprShiftImm(SDOperand N, unsigned& Opc, unsigned& SH) {
@@ -675,8 +682,7 @@
// isOprNot - Returns true if the specified operand is an xor with
immediate -1.
static bool isOprNot(SDOperand N) {
unsigned Imm;
- return N.getOpcode() == ISD::XOR &&
- isIntImmediate(N.getOperand(1), Imm) && (signed)Imm == -1;
+ return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
}
// Immediate constant composers.
@@ -1089,10 +1095,8 @@
/// wider than the implicit mask, then we can get rid of the AND and
let the
/// shift do the mask.
unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
- unsigned C, MB, ME;
- if (N.getOpcode() == ISD::AND &&
- isIntImmediate(N.getOperand(1), C) && isRunOfOnes(C, MB, ME) &&
- MB <= 26 && ME == 31)
+ unsigned C;
+ if (isOpcWithIntImmediate(N, ISD::AND, C) && isMask_32(C) && C > 63)
return SelectExpr(N.getOperand(0));
else
return SelectExpr(N);
@@ -1580,35 +1584,62 @@
return Result;
case ISD::SHL:
- Tmp1 = SelectExpr(N.getOperand(0));
if (isIntImmediate(N.getOperand(1), Tmp2)) {
+ unsigned SH, MB, ME;
+ if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
+ isRotateAndMask(ISD::SHL, Tmp2, Tmp3, true, SH, MB, ME)) {
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
+ .addImm(MB).addImm(ME);
+ return Result;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 &= 0x1F;
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm
(Tmp2).addImm(0)
.addImm(31-Tmp2);
} else {
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
case ISD::SRL:
- Tmp1 = SelectExpr(N.getOperand(0));
if (isIntImmediate(N.getOperand(1), Tmp2)) {
+ unsigned SH, MB, ME;
+ if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
+ isRotateAndMask(ISD::SRL, Tmp2, Tmp3, true, SH, MB, ME)) {
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
+ .addImm(MB).addImm(ME);
+ return Result;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 &= 0x1F;
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(32-Tmp2)
.addImm(Tmp2).addImm(31);
} else {
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
case ISD::SRA:
- Tmp1 = SelectExpr(N.getOperand(0));
if (isIntImmediate(N.getOperand(1), Tmp2)) {
+ unsigned SH, MB, ME;
+ if (isOpcWithIntImmediate(N.getOperand(0), ISD::AND, Tmp3) &&
+ isRotateAndMask(ISD::SRA, Tmp2, Tmp3, true, SH, MB, ME)) {
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(SH)
+ .addImm(MB).addImm(ME);
+ return Result;
+ }
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 &= 0x1F;
BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
} else {
+ Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
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