[llvm-commits] CVS: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp DependenceAnalyzer.h MSSchedule.cpp MSSchedule.h MSScheduleSB.cpp MSScheduleSB.h MSchedGraph.cpp MSchedGraph.h MSchedGraphSB.cpp MSchedGraphSB.h ModuloScheduling.cpp ModuloScheduling.h ModuloSchedulingSuperBlock.cpp ModuloSchedulingSuperBlock.h
Jeff Cohen
jeffc at jolt-lang.org
Tue Jul 26 22:54:01 PDT 2005
Changes in directory llvm/lib/Target/SparcV9/ModuloScheduling:
DependenceAnalyzer.cpp updated: 1.7 -> 1.8
DependenceAnalyzer.h updated: 1.3 -> 1.4
MSSchedule.cpp updated: 1.16 -> 1.17
MSSchedule.h updated: 1.7 -> 1.8
MSScheduleSB.cpp updated: 1.1 -> 1.2
MSScheduleSB.h updated: 1.1 -> 1.2
MSchedGraph.cpp updated: 1.21 -> 1.22
MSchedGraph.h updated: 1.14 -> 1.15
MSchedGraphSB.cpp updated: 1.3 -> 1.4
MSchedGraphSB.h updated: 1.1 -> 1.2
ModuloScheduling.cpp updated: 1.50 -> 1.51
ModuloScheduling.h updated: 1.31 -> 1.32
ModuloSchedulingSuperBlock.cpp updated: 1.3 -> 1.4
ModuloSchedulingSuperBlock.h updated: 1.2 -> 1.3
---
Log message:
Eliminate tabs and trailing spaces.
---
Diffs of the changes: (+2995 -2995)
DependenceAnalyzer.cpp | 44
DependenceAnalyzer.h | 28
MSSchedule.cpp | 74 -
MSSchedule.h | 2
MSScheduleSB.cpp | 76 -
MSScheduleSB.h | 2
MSchedGraph.cpp | 516 ++++----
MSchedGraph.h | 56
MSchedGraphSB.cpp | 576 ++++-----
MSchedGraphSB.h | 64 -
ModuloScheduling.cpp | 1854 +++++++++++++++---------------
ModuloScheduling.h | 38
ModuloSchedulingSuperBlock.cpp | 2494 ++++++++++++++++++++---------------------
ModuloSchedulingSuperBlock.h | 166 +-
14 files changed, 2995 insertions(+), 2995 deletions(-)
Index: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.7 llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.8
--- llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp:1.7 Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.cpp Wed Jul 27 00:53:44 2005
@@ -31,9 +31,9 @@
Statistic<> NoDeps("depanalyzer-nodeps", "Number of dependences eliminated");
Statistic<> NumDeps("depanalyzer-deps",
- "Number of dependences could not eliminate");
+ "Number of dependences could not eliminate");
Statistic<> AdvDeps("depanalyzer-advdeps",
- "Number of dependences using advanced techniques");
+ "Number of dependences using advanced techniques");
bool DependenceAnalyzer::runOnFunction(Function &F) {
AA = &getAnalysis<AliasAnalysis>();
@@ -44,7 +44,7 @@
}
static RegisterAnalysis<DependenceAnalyzer>X("depanalyzer",
- "Dependence Analyzer");
+ "Dependence Analyzer");
// - Get inter and intra dependences between loads and stores
//
@@ -57,10 +57,10 @@
// further (Step 4)
// Step 4: do advanced analysis
void DependenceAnalyzer::AnalyzeDeps(Value *val, Value *val2, bool valLoad,
- bool val2Load,
- std::vector<Dependence> &deps,
- BasicBlock *BB,
- bool srcBeforeDest) {
+ bool val2Load,
+ std::vector<Dependence> &deps,
+ BasicBlock *BB,
+ bool srcBeforeDest) {
bool loopInvariant = true;
@@ -76,7 +76,7 @@
//If Loop invariant, let AA decide
if(loopInvariant) {
if(AA->alias(val, (unsigned)TD->getTypeSize(val->getType()),
- val2,(unsigned)TD->getTypeSize(val2->getType()))
+ val2,(unsigned)TD->getTypeSize(val2->getType()))
!= AliasAnalysis::NoAlias) {
createDep(deps, valLoad, val2Load, srcBeforeDest);
}
@@ -102,7 +102,7 @@
Value *GPop = GP->getOperand(0);
Value *GP2op = GP2->getOperand(0);
int alias = AA->alias(GPop, (unsigned)TD->getTypeSize(GPop->getType()),
- GP2op,(unsigned)TD->getTypeSize(GP2op->getType()));
+ GP2op,(unsigned)TD->getTypeSize(GP2op->getType()));
if(alias == AliasAnalysis::MustAlias) {
@@ -121,11 +121,11 @@
// advancedDepAnalysis - Do advanced data dependence tests
void DependenceAnalyzer::advancedDepAnalysis(GetElementPtrInst *gp1,
- GetElementPtrInst *gp2,
- bool valLoad,
- bool val2Load,
- std::vector<Dependence> &deps,
- bool srcBeforeDest) {
+ GetElementPtrInst *gp2,
+ bool valLoad,
+ bool val2Load,
+ std::vector<Dependence> &deps,
+ bool srcBeforeDest) {
//Check if both GEPs are in a simple form: 3 ops, constant 0 as second arg
if(gp1->getNumOperands() != 3 || gp2->getNumOperands() != 3) {
@@ -138,7 +138,7 @@
if(Constant *c1 = dyn_cast<Constant>(gp1->getOperand(1)))
if(Constant *c2 = dyn_cast<Constant>(gp2->getOperand(1)))
if(c1->isNullValue() && c2->isNullValue())
- GPok = true;
+ GPok = true;
if(!GPok) {
createDep(deps, valLoad, val2Load, srcBeforeDest);
@@ -230,8 +230,8 @@
// Create dependences once its determined these two instructions
// references the same memory
void DependenceAnalyzer::createDep(std::vector<Dependence> &deps,
- bool valLoad, bool val2Load,
- bool srcBeforeDest, int diff) {
+ bool valLoad, bool val2Load,
+ bool srcBeforeDest, int diff) {
//If the source instruction occurs after the destination instruction
//(execution order), then this dependence is across iterations
@@ -269,8 +269,8 @@
//Get Dependence Info for a pair of Instructions
DependenceResult DependenceAnalyzer::getDependenceInfo(Instruction *inst1,
- Instruction *inst2,
- bool srcBeforeDest) {
+ Instruction *inst2,
+ bool srcBeforeDest) {
std::vector<Dependence> deps;
DEBUG(std::cerr << "Inst1: " << *inst1 << "\n");
@@ -284,17 +284,17 @@
if(StoreInst *stInst = dyn_cast<StoreInst>(inst2))
AnalyzeDeps(ldInst->getOperand(0), stInst->getOperand(1),
- true, false, deps, ldInst->getParent(), srcBeforeDest);
+ true, false, deps, ldInst->getParent(), srcBeforeDest);
}
else if(StoreInst *stInst = dyn_cast<StoreInst>(inst1)) {
if(LoadInst *ldInst = dyn_cast<LoadInst>(inst2))
AnalyzeDeps(stInst->getOperand(1), ldInst->getOperand(0), false, true,
- deps, ldInst->getParent(), srcBeforeDest);
+ deps, ldInst->getParent(), srcBeforeDest);
else if(StoreInst *stInst2 = dyn_cast<StoreInst>(inst2))
AnalyzeDeps(stInst->getOperand(1), stInst2->getOperand(1), false, false,
- deps, stInst->getParent(), srcBeforeDest);
+ deps, stInst->getParent(), srcBeforeDest);
}
else
assert(0 && "Expected a load or a store\n");
Index: llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h:1.3 llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h:1.4
--- llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h:1.3 Fri Apr 22 01:32:48 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/DependenceAnalyzer.h Wed Jul 27 00:53:44 2005
@@ -22,7 +22,7 @@
#include <vector>
namespace llvm {
-
+
//class to represent a dependence
struct Dependence {
@@ -49,22 +49,22 @@
class DependenceAnalyzer : public FunctionPass {
-
+
AliasAnalysis *AA;
TargetData *TD;
ScalarEvolution *SE;
- void advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2,
- bool valLoad, bool val2Load,
- std::vector<Dependence> &deps, bool srcBeforeDest);
-
- void AnalyzeDeps(Value *val, Value *val2, bool val1Load, bool val2Load,
- std::vector<Dependence> &deps, BasicBlock *BB,
- bool srcBeforeDest);
-
- void createDep(std::vector<Dependence> &deps, bool valLoad, bool val2Load,
- bool srcBeforeDest, int diff = 0);
+ void advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2,
+ bool valLoad, bool val2Load,
+ std::vector<Dependence> &deps, bool srcBeforeDest);
+
+ void AnalyzeDeps(Value *val, Value *val2, bool val1Load, bool val2Load,
+ std::vector<Dependence> &deps, BasicBlock *BB,
+ bool srcBeforeDest);
+
+ void createDep(std::vector<Dependence> &deps, bool valLoad, bool val2Load,
+ bool srcBeforeDest, int diff = 0);
public:
DependenceAnalyzer() { AA = 0; TD = 0; SE = 0; }
@@ -80,8 +80,8 @@
}
//get dependence info
- DependenceResult getDependenceInfo(Instruction *inst1, Instruction *inst2,
- bool srcBeforeDest);
+ DependenceResult getDependenceInfo(Instruction *inst1, Instruction *inst2,
+ bool srcBeforeDest);
};
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.16 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.17
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp:1.16 Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.cpp Wed Jul 27 00:53:44 2005
@@ -33,10 +33,10 @@
if (schedule[cycle].size() < numIssue) {
//Now check if all the resources in their respective cycles are available
if(resourcesFree(node, cycle, II)) {
- //Insert to preserve dependencies
- addToSchedule(cycle,node);
- DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
- return false;
+ //Insert to preserve dependencies
+ addToSchedule(cycle,node);
+ DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
+ return false;
}
}
}
@@ -81,7 +81,7 @@
if(resourceNumPerCycle[cycle].count(resourceNum)) {
int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers;
if(resourceNumPerCycle[cycle][resourceNum] >= maxRes)
- isFree = false;
+ isFree = false;
}
}
@@ -137,21 +137,21 @@
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
-
- //Get Resource to check its availability
- int resourceNum = resources[i][j];
-
- DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
-
- success = resourceAvailable(resourceNum, currentCycle);
-
- if(!success)
- break;
-
+
+ //Get Resource to check its availability
+ int resourceNum = resources[i][j];
+
+ DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
+
+ success = resourceAvailable(resourceNum, currentCycle);
+
+ if(!success)
+ break;
+
}
if(!success)
- break;
+ break;
//Increase cycle
currentCycle++;
@@ -172,8 +172,8 @@
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
- int resourceNum = resources[i][j];
- useResource(resourceNum, currentCycle);
+ int resourceNum = resources[i][j];
+ useResource(resourceNum, currentCycle);
}
currentCycle++;
}
@@ -205,15 +205,15 @@
int count = 0;
for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
if(schedule.count(i)) {
- for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
- E = schedule[i].end(); I != E; ++I) {
- //Check if its a branch
- assert(!(*I)->isBranch() && "Branch should not be schedule!");
-
- tempKernel.push_back(std::make_pair(*I, count));
- maxSN = std::max(maxSN, count);
-
- }
+ for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
+ E = schedule[i].end(); I != E; ++I) {
+ //Check if its a branch
+ assert(!(*I)->isBranch() && "Branch should not be schedule!");
+
+ tempKernel.push_back(std::make_pair(*I, count));
+ maxSN = std::max(maxSN, count);
+
+ }
}
++count;
}
@@ -231,14 +231,14 @@
for(std::map<const MachineInstr*, unsigned>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
- if(N->second < I->first->getIndex())
- tmpMap[N->second] = (MachineInstr*) N->first;
+ if(N->second < I->first->getIndex())
+ tmpMap[N->second] = (MachineInstr*) N->first;
}
//Add to kernel, and delete from indVar
for(std::map<unsigned, MachineInstr*>::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) {
- kernel.push_back(std::make_pair(N->second, 0));
- indVar.erase(N->second);
+ kernel.push_back(std::make_pair(N->second, 0));
+ indVar.erase(N->second);
}
}
@@ -278,10 +278,10 @@
const MachineOperand &mOp = inst->getOperand(i);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
if(def == mOp.getVRegValue()) {
- if(P->second >= stage)
- return false;
- else
- return true;
+ if(P->second >= stage)
+ return false;
+ else
+ return true;
}
}
}
@@ -302,7 +302,7 @@
os << "Kernel:\n";
for(std::vector<std::pair<MachineInstr*, int> >::const_iterator I = kernel.begin(),
- E = kernel.end(); I != E; ++I)
+ E = kernel.end(); I != E; ++I)
os << "Node: " << *(I->first) << " Stage: " << I->second << "\n";
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.7 llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.8
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h:1.7 Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSSchedule.h Wed Jul 27 00:53:44 2005
@@ -28,7 +28,7 @@
std::map<int, std::map<int, int> > resourceNumPerCycle;
//Check if all resources are free
- bool resourcesFree(MSchedGraphNode*, int, int II);
+ bool resourcesFree(MSchedGraphNode*, int, int II);
bool resourceAvailable(int resourceNum, int cycle);
void useResource(int resourceNum, int cycle);
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.2
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp:1.1 Thu Jun 16 23:15:43 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.cpp Wed Jul 27 00:53:44 2005
@@ -33,10 +33,10 @@
if (schedule[cycle].size() < numIssue) {
//Now check if all the resources in their respective cycles are available
if(resourcesFree(node, cycle, II)) {
- //Insert to preserve dependencies
- addToSchedule(cycle,node);
- DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
- return false;
+ //Insert to preserve dependencies
+ addToSchedule(cycle,node);
+ DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
+ return false;
}
}
}
@@ -81,7 +81,7 @@
if(resourceNumPerCycle[cycle].count(resourceNum)) {
int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers;
if(resourceNumPerCycle[cycle][resourceNum] >= maxRes)
- isFree = false;
+ isFree = false;
}
}
@@ -137,21 +137,21 @@
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
-
- //Get Resource to check its availability
- int resourceNum = resources[i][j];
-
- DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
-
- success = resourceAvailable(resourceNum, currentCycle);
-
- if(!success)
- break;
-
+
+ //Get Resource to check its availability
+ int resourceNum = resources[i][j];
+
+ DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
+
+ success = resourceAvailable(resourceNum, currentCycle);
+
+ if(!success)
+ break;
+
}
if(!success)
- break;
+ break;
//Increase cycle
currentCycle++;
@@ -172,8 +172,8 @@
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
- int resourceNum = resources[i][j];
- useResource(resourceNum, currentCycle);
+ int resourceNum = resources[i][j];
+ useResource(resourceNum, currentCycle);
}
currentCycle++;
}
@@ -205,15 +205,15 @@
int count = 0;
for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
if(schedule.count(i)) {
- for(std::vector<MSchedGraphSBNode*>::iterator I = schedule[i].begin(),
- E = schedule[i].end(); I != E; ++I) {
- //Check if its a branch
- assert(!(*I)->isBranch() && "Branch should not be schedule!");
-
- tempKernel.push_back(std::make_pair(*I, count));
- maxSN = std::max(maxSN, count);
-
- }
+ for(std::vector<MSchedGraphSBNode*>::iterator I = schedule[i].begin(),
+ E = schedule[i].end(); I != E; ++I) {
+ //Check if its a branch
+ assert(!(*I)->isBranch() && "Branch should not be schedule!");
+
+ tempKernel.push_back(std::make_pair(*I, count));
+ maxSN = std::max(maxSN, count);
+
+ }
}
++count;
}
@@ -231,14 +231,14 @@
for(std::map<const MachineInstr*, unsigned>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
- if(N->second < I->first->getIndex())
- tmpMap[N->second] = (MachineInstr*) N->first;
+ if(N->second < I->first->getIndex())
+ tmpMap[N->second] = (MachineInstr*) N->first;
}
//Add to kernel, and delete from indVar
for(std::map<unsigned, MachineInstr*>::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) {
- kernel.push_back(std::make_pair(N->second, 0));
- indVar.erase(N->second);
+ kernel.push_back(std::make_pair(N->second, 0));
+ indVar.erase(N->second);
}
}
@@ -247,7 +247,7 @@
//assert(I->second == 0 && "Predicate node must be from current iteration\n");
std::vector<const MachineInstr*> otherInstrs = I->first->getOtherInstrs();
for(std::vector<const MachineInstr*>::iterator O = otherInstrs.begin(), OE = otherInstrs.end(); O != OE; ++O) {
- kernel.push_back(std::make_pair((MachineInstr*) *O, I->second));
+ kernel.push_back(std::make_pair((MachineInstr*) *O, I->second));
}
}
@@ -285,10 +285,10 @@
const MachineOperand &mOp = inst->getOperand(i);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
if(def == mOp.getVRegValue()) {
- if(P->second >= stage)
- return false;
- else
- return true;
+ if(P->second >= stage)
+ return false;
+ else
+ return true;
}
}
}
@@ -309,7 +309,7 @@
os << "Kernel:\n";
for(std::vector<std::pair<MachineInstr*, int> >::const_iterator I = kernel.begin(),
- E = kernel.end(); I != E; ++I)
+ E = kernel.end(); I != E; ++I)
os << "Node: " << *(I->first) << " Stage: " << I->second << "\n";
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.2
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h:1.1 Thu Jun 16 23:15:43 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSScheduleSB.h Wed Jul 27 00:53:44 2005
@@ -28,7 +28,7 @@
std::map<int, std::map<int, int> > resourceNumPerCycle;
//Check if all resources are free
- bool resourcesFree(MSchedGraphSBNode*, int, int II);
+ bool resourcesFree(MSchedGraphSBNode*, int, int II);
bool resourceAvailable(int resourceNum, int cycle);
void useResource(int resourceNum, int cycle);
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.21 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.22
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp:1.21 Sat Apr 30 20:25:53 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.cpp Wed Jul 27 00:53:44 2005
@@ -33,8 +33,8 @@
//MSchedGraphNode constructor
MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst,
- MSchedGraph *graph, unsigned idx,
- unsigned late, bool isBranch)
+ MSchedGraph *graph, unsigned idx,
+ unsigned late, bool isBranch)
: Inst(inst), Parent(graph), index(idx), latency(late),
isBranchInstr(isBranch) {
@@ -76,7 +76,7 @@
//Get the iteration difference for the edge from this node to its successor
unsigned MSchedGraphNode::getIteDiff(MSchedGraphNode *succ) {
for(std::vector<MSchedGraphEdge>::iterator I = Successors.begin(),
- E = Successors.end();
+ E = Successors.end();
I != E; ++I) {
if(I->getDest() == succ)
return I->getIteDiff();
@@ -90,7 +90,7 @@
//return the edge the corresponds to this in edge
int count = 0;
for(MSchedGraphNode::succ_iterator I = pred->succ_begin(),
- E = pred->succ_end();
+ E = pred->succ_end();
I != E; ++I) {
if(*I == this)
return count;
@@ -111,7 +111,7 @@
//Dtermine if pred is a predecessor of this node
bool MSchedGraphNode::isPredecessor(MSchedGraphNode *pred) {
if(std::find( Predecessors.begin(), Predecessors.end(),
- pred) != Predecessors.end())
+ pred) != Predecessors.end())
return true;
else
return false;
@@ -119,11 +119,11 @@
//Add a node to the graph
void MSchedGraph::addNode(const MachineInstr *MI,
- MSchedGraphNode *node) {
+ MSchedGraphNode *node) {
//Make sure node does not already exist
assert(GraphMap.find(MI) == GraphMap.end()
- && "New MSchedGraphNode already exists for this instruction");
+ && "New MSchedGraphNode already exists for this instruction");
GraphMap[MI] = node;
}
@@ -149,10 +149,10 @@
//is a special case in Modulo Scheduling. We only want to deal with
//the body of the loop.
MSchedGraph::MSchedGraph(const MachineBasicBlock *bb,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm)
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm)
: Target(targ) {
//Make sure BB is not null,
@@ -172,10 +172,10 @@
//is a special case in Modulo Scheduling. We only want to deal with
//the body of the loop.
MSchedGraph::MSchedGraph(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm)
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm)
: BBs(bbs), Target(targ) {
//Make sure there is at least one BB and it is not null,
@@ -191,7 +191,7 @@
//Copies the graph and keeps a map from old to new nodes
MSchedGraph::MSchedGraph(const MSchedGraph &G,
- std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
+ std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
: Target(G.Target) {
BBs = G.BBs;
@@ -199,7 +199,7 @@
std::map<MSchedGraphNode*, MSchedGraphNode*> oldToNew;
//Copy all nodes
for(MSchedGraph::const_iterator N = G.GraphMap.begin(),
- NE = G.GraphMap.end(); N != NE; ++N) {
+ NE = G.GraphMap.end(); N != NE; ++N) {
MSchedGraphNode *newNode = new MSchedGraphNode(*(N->second));
oldToNew[&*(N->second)] = newNode;
@@ -272,8 +272,8 @@
}
//Experimental code to add edges from the branch to all nodes dependent upon it.
void hasPath(MSchedGraphNode *node, std::set<MSchedGraphNode*> &visited,
- std::set<MSchedGraphNode*> &branches, MSchedGraphNode *startNode,
- std::set<std::pair<MSchedGraphNode*,MSchedGraphNode*> > &newEdges ) {
+ std::set<MSchedGraphNode*> &branches, MSchedGraphNode *startNode,
+ std::set<std::pair<MSchedGraphNode*,MSchedGraphNode*> > &newEdges ) {
visited.insert(node);
DEBUG(std::cerr << "Visiting: " << *node << "\n");
@@ -287,7 +287,7 @@
//only visit if we have not already
else if(!visited.count(dest)) {
if(edge->getIteDiff() == 0)
- hasPath(dest, visited, branches, startNode, newEdges);}
+ hasPath(dest, visited, branches, startNode, newEdges);}
}
@@ -302,7 +302,7 @@
I != E; ++I) {
if(I->second->isBranch())
if(I->second->hasPredecessors())
- branches.insert(I->second);
+ branches.insert(I->second);
}
//See if there is a path first instruction to the branches, if so, add an
@@ -318,8 +318,8 @@
unsigned min = GraphMap.size();
if(newEdges.size() == 1) {
((newEdges.begin())->first)->addOutEdge(((newEdges.begin())->second),
- MSchedGraphEdge::BranchDep,
- MSchedGraphEdge::NonDataDep, 1);
+ MSchedGraphEdge::BranchDep,
+ MSchedGraphEdge::NonDataDep, 1);
}
else {
@@ -331,13 +331,13 @@
DEBUG(std::cerr << "Branch Edge from: " << *(I->first) << " to " << *(I->second) << "\n");
// if(I->second->getIndex() <= min) {
- start = I->first;
- end = I->second;
- //min = I->second->getIndex();
- //}
- start->addOutEdge(end,
- MSchedGraphEdge::BranchDep,
- MSchedGraphEdge::NonDataDep, 1);
+ start = I->first;
+ end = I->second;
+ //min = I->second->getIndex();
+ //}
+ start->addOutEdge(end,
+ MSchedGraphEdge::BranchDep,
+ MSchedGraphEdge::NonDataDep, 1);
}
}
}
@@ -345,8 +345,8 @@
//Add edges between the nodes
void MSchedGraph::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Machine target information for calculating latency
@@ -361,18 +361,18 @@
unsigned index = 0;
for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
- BE = BBs.end(); B != BE; ++B) {
+ BE = BBs.end(); B != BE; ++B) {
const MachineBasicBlock *BB = *B;
//Loop over instructions in MBB and add nodes and edges
for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
- MI != e; ++MI) {
+ MI != e; ++MI) {
//Ignore indvar instructions
if(ignoreInstrs.count(MI)) {
- ++index;
- continue;
+ ++index;
+ continue;
}
//Get each instruction of machine basic block, get the delay
@@ -386,16 +386,16 @@
//Check if subsequent instructions can be issued before
//the result is ready, if so use min delay.
if(MTI->hasResultInterlock(MIopCode))
- delay = MTI->minLatency(MIopCode);
+ delay = MTI->minLatency(MIopCode);
else
#endif
- //Get delay
- delay = MTI->maxLatency(opCode);
+ //Get delay
+ delay = MTI->maxLatency(opCode);
//Create new node for this machine instruction and add to the graph.
//Create only if not a nop
if(MTI->isNop(opCode))
- continue;
+ continue;
//Sparc BE does not use PHI opcode, so assert on this case
assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
@@ -404,74 +404,74 @@
//We want to flag the branch node to treat it special
if(MTI->isBranch(opCode))
- isBranch = true;
+ isBranch = true;
//Node is created and added to the graph automatically
MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
- isBranch);
+ isBranch);
DEBUG(std::cerr << "Created Node: " << *node << "\n");
//Check OpCode to keep track of memory operations to add memory
//dependencies later.
if(MTI->isLoad(opCode) || MTI->isStore(opCode))
- memInstructions.push_back(node);
+ memInstructions.push_back(node);
//Loop over all operands, and put them into the register number to
//graph node map for determining dependencies
//If an operands is a use/def, we have an anti dependence to itself
for(unsigned i=0; i < MI->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = MI->getOperand(i);
-
- //Check if it has an allocated register
- if(mOp.hasAllocatedReg()) {
- int regNum = mOp.getReg();
-
- if(regNum != SparcV9::g0) {
- //Put into our map
- regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
- }
- continue;
- }
-
-
- //Add virtual registers dependencies
- //Check if any exist in the value map already and create dependencies
- //between them.
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) {
-
- //Make sure virtual register value is not null
- assert((mOp.getVRegValue() != NULL) && "Null value is defined");
-
- //Check if this is a read operation in a phi node, if so DO NOT PROCESS
- if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
- DEBUG(std::cerr << "Read Operation in a PHI node\n");
- continue;
- }
-
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
-
- //Add to value map
- V->second.push_back(std::make_pair(i,node));
- }
- //Otherwise put it in the map
- else
- //Put into value map
- valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = MI->getOperand(i);
+
+ //Check if it has an allocated register
+ if(mOp.hasAllocatedReg()) {
+ int regNum = mOp.getReg();
+
+ if(regNum != SparcV9::g0) {
+ //Put into our map
+ regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
+ }
+ continue;
+ }
+
+
+ //Add virtual registers dependencies
+ //Check if any exist in the value map already and create dependencies
+ //between them.
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) {
+
+ //Make sure virtual register value is not null
+ assert((mOp.getVRegValue() != NULL) && "Null value is defined");
+
+ //Check if this is a read operation in a phi node, if so DO NOT PROCESS
+ if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
+ DEBUG(std::cerr << "Read Operation in a PHI node\n");
+ continue;
+ }
+
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
+
+ //Add to value map
+ V->second.push_back(std::make_pair(i,node));
+ }
+ //Otherwise put it in the map
+ else
+ //Put into value map
+ valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
+ }
+ }
}
++index;
}
@@ -480,15 +480,15 @@
//phiInstr list to process
const BasicBlock *llvm_bb = BB->getBasicBlock();
for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
- I != E; ++I) {
+ I != E; ++I) {
if(const PHINode *PN = dyn_cast<PHINode>(I)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- if(!ignoreInstrs.count(tempMvec[j])) {
- DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
- phiInstrs.push_back((MachineInstr*) tempMvec[j]);
- }
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ if(!ignoreInstrs.count(tempMvec[j])) {
+ DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
+ phiInstrs.push_back((MachineInstr*) tempMvec[j]);
+ }
+ }
}
}
@@ -498,14 +498,14 @@
//Finally deal with PHI Nodes and Value*
for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
- E = phiInstrs.end(); I != E; ++I) {
+ E = phiInstrs.end(); I != E; ++I) {
//Get Node for this instruction
std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
X = find(*I);
if(X == GraphMap.end())
- continue;
+ continue;
MSchedGraphNode *node = X->second;
@@ -513,38 +513,38 @@
//Loop over operands for this instruction and add value edges
for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = (*I)->getOperand(i);
- if((mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
-
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
- phiInstrs, 1);
- }
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = (*I)->getOperand(i);
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
+
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
+ phiInstrs, 1);
+ }
+ }
+ }
}
}
}
}
//Add dependencies for Value*s
void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphNode *destNode, bool nodeIsUse,
- bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
+ MSchedGraphNode *destNode, bool nodeIsUse,
+ bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
- E = NodesInMap.end(); I != E; ++I) {
+ E = NodesInMap.end(); I != E; ++I) {
//Get node in vectors machine operand that is the same value as node
MSchedGraphNode *srcNode = I->second;
@@ -552,26 +552,26 @@
if(diff > 0)
if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
- continue;
+ continue;
//Node is a Def, so add output dep.
if(nodeIsDef) {
if(mOp.isUse()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
- MSchedGraphEdge::AntiDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ MSchedGraphEdge::AntiDep, diff);
}
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
- MSchedGraphEdge::OutputDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ MSchedGraphEdge::OutputDep, diff);
}
}
if(nodeIsUse) {
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
- MSchedGraphEdge::TrueDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ MSchedGraphEdge::TrueDep, diff);
}
}
}
@@ -609,71 +609,71 @@
//Look at all instructions after this in execution order
for(unsigned j=i+1; j < Nodes.size(); ++j) {
-
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep);
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep);
+
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::TrueDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::TrueDep);
+ }
}
//Look at all the instructions before this one since machine registers
//could live across iterations.
for(unsigned j = 0; j < i; ++j) {
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep, 1);
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep, 1);
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep, 1);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep, 1);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep, 1);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep, 1);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep, 1);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::TrueDep,1 );
- }
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep, 1);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::TrueDep,1 );
+ }
+
}
@@ -686,8 +686,8 @@
//Add edges between all loads and stores
//Can be less strict with alias analysis and data dependence analysis.
void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Target machine instruction info
const TargetInstrInfo *TMI = Target.getInstrInfo();
@@ -707,7 +707,7 @@
//No self loops
if(destIndex == srcIndex)
- continue;
+ continue;
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
@@ -717,7 +717,7 @@
//Assuming instructions without corresponding llvm instructions
//are from constant pools.
if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
- continue;
+ continue;
bool useDepAnalyzer = true;
@@ -726,78 +726,78 @@
Instruction *srcLLVM = machineTollvm[srcInst];
Instruction *destLLVM = machineTollvm[destInst];
if(!isa<LoadInst>(srcLLVM)
- && !isa<StoreInst>(srcLLVM)) {
- if(isa<BinaryOperator>(srcLLVM)) {
- if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(srcLLVM)) {
+ if(isa<BinaryOperator>(srcLLVM)) {
+ if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
if(!isa<LoadInst>(destLLVM)
- && !isa<StoreInst>(destLLVM)) {
- if(isa<BinaryOperator>(destLLVM)) {
- if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(destLLVM)) {
+ if(isa<BinaryOperator>(destLLVM)) {
+ if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
//Use dep analysis when we have corresponding llvm loads/stores
if(useDepAnalyzer) {
- bool srcBeforeDest = true;
- if(destIndex < srcIndex)
- srcBeforeDest = false;
-
- DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
- machineTollvm[destInst],
- srcBeforeDest);
-
- for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
- de = dr.dependences.end(); d != de; ++d) {
- //Add edge from load to store
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- d->getDepType(), d->getIteDiff());
-
- }
+ bool srcBeforeDest = true;
+ if(destIndex < srcIndex)
+ srcBeforeDest = false;
+
+ DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
+ machineTollvm[destInst],
+ srcBeforeDest);
+
+ for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
+ de = dr.dependences.end(); d != de; ++d) {
+ //Add edge from load to store
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ d->getDepType(), d->getIteDiff());
+
+ }
}
//Otherwise, we can not do any further analysis and must make a dependence
else {
-
- //Get the machine opCode to determine type of memory instruction
- MachineOpCode destNodeOpCode = destInst->getOpcode();
-
- //Get the Value* that we are reading from the load, always the first op
- const MachineOperand &mOp = srcInst->getOperand(0);
- const MachineOperand &mOp2 = destInst->getOperand(0);
-
- if(mOp.hasAllocatedReg())
- if(mOp.getReg() == SparcV9::g0)
- continue;
- if(mOp2.hasAllocatedReg())
- if(mOp2.getReg() == SparcV9::g0)
- continue;
-
- DEBUG(std::cerr << "Adding dependence for machine instructions\n");
- //Load-Store deps
- if(TMI->isLoad(srcNodeOpCode)) {
-
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- MSchedGraphEdge::AntiDep, 0);
- }
- else if(TMI->isStore(srcNodeOpCode)) {
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- MSchedGraphEdge::OutputDep, 0);
-
- else
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- MSchedGraphEdge::TrueDep, 0);
- }
+
+ //Get the machine opCode to determine type of memory instruction
+ MachineOpCode destNodeOpCode = destInst->getOpcode();
+
+ //Get the Value* that we are reading from the load, always the first op
+ const MachineOperand &mOp = srcInst->getOperand(0);
+ const MachineOperand &mOp2 = destInst->getOperand(0);
+
+ if(mOp.hasAllocatedReg())
+ if(mOp.getReg() == SparcV9::g0)
+ continue;
+ if(mOp2.hasAllocatedReg())
+ if(mOp2.getReg() == SparcV9::g0)
+ continue;
+
+ DEBUG(std::cerr << "Adding dependence for machine instructions\n");
+ //Load-Store deps
+ if(TMI->isLoad(srcNodeOpCode)) {
+
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ MSchedGraphEdge::AntiDep, 0);
+ }
+ else if(TMI->isStore(srcNodeOpCode)) {
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ MSchedGraphEdge::OutputDep, 0);
+
+ else
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ MSchedGraphEdge::TrueDep, 0);
+ }
}
}
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h:1.14 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h:1.15
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h:1.14 Sat Apr 30 20:25:53 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraph.h Wed Jul 27 00:53:44 2005
@@ -54,7 +54,7 @@
private:
friend class MSchedGraphNode;
MSchedGraphEdge(MSchedGraphNode *destination, MSchedGraphEdgeType type,
- unsigned deptype, unsigned diff)
+ unsigned deptype, unsigned diff)
: dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {}
MSchedGraphNode *dest;
@@ -79,7 +79,7 @@
public:
MSchedGraphNode(const MachineInstr *inst, MSchedGraph *graph,
- unsigned index, unsigned late=0, bool isBranch=false);
+ unsigned index, unsigned late=0, bool isBranch=false);
MSchedGraphNode(const MSchedGraphNode &N);
@@ -94,12 +94,12 @@
pred_const_iterator pred_end() const { return Predecessors.end(); }
typedef MSchedGraphNodeIterator<std::vector<MSchedGraphEdge>::const_iterator,
- const MSchedGraphNode> succ_const_iterator;
+ const MSchedGraphNode> succ_const_iterator;
succ_const_iterator succ_begin() const;
succ_const_iterator succ_end() const;
typedef MSchedGraphNodeIterator<std::vector<MSchedGraphEdge>::iterator,
- MSchedGraphNode> succ_iterator;
+ MSchedGraphNode> succ_iterator;
succ_iterator succ_begin();
succ_iterator succ_end();
unsigned succ_size() { return Successors.size(); }
@@ -119,17 +119,17 @@
void deleteSuccessor(MSchedGraphNode *node) {
for (unsigned i = 0; i != Successors.size(); ++i)
- if (Successors[i].getDest() == node) {
- Successors.erase(Successors.begin()+i);
- node->Predecessors.erase(std::find(node->Predecessors.begin(),
- node->Predecessors.end(), this));
- --i; //Decrease index var since we deleted a node
- }
+ if (Successors[i].getDest() == node) {
+ Successors.erase(Successors.begin()+i);
+ node->Predecessors.erase(std::find(node->Predecessors.begin(),
+ node->Predecessors.end(), this));
+ --i; //Decrease index var since we deleted a node
+ }
}
void addOutEdge(MSchedGraphNode *destination,
- MSchedGraphEdge::MSchedGraphEdgeType type,
- unsigned deptype, unsigned diff=0) {
+ MSchedGraphEdge::MSchedGraphEdgeType type,
+ unsigned deptype, unsigned diff=0) {
Successors.push_back(MSchedGraphEdge(destination, type, deptype,diff));
destination->Predecessors.push_back(this);
}
@@ -205,7 +205,7 @@
// ostream << operator for MSGraphNode class
inline std::ostream &operator<<(std::ostream &os,
- const MSchedGraphNode &node) {
+ const MSchedGraphNode &node) {
node.print(os);
return os;
}
@@ -243,27 +243,27 @@
typedef std::pair<int, MSchedGraphNode*> OpIndexNodePair;
void buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphNode *node,
- bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
+ MSchedGraphNode *node,
+ bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
void addMachRegEdges(std::map<int,
- std::vector<OpIndexNodePair> >& regNumtoNodeMap);
+ std::vector<OpIndexNodePair> >& regNumtoNodeMap);
void addMemEdges(const std::vector<MSchedGraphNode*>& memInst,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
void addBranchEdges();
public:
MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
//Copy constructor with maps to link old nodes to new nodes
MSchedGraph(const MSchedGraph &G, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
-
- MSchedGraph(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm);
+
+ MSchedGraph(std::vector<const MachineBasicBlock*> &bbs,
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm);
//Print graph
void print(std::ostream &os) const;
@@ -299,7 +299,7 @@
// Provide specializations of GraphTraits to be able to use graph
// iterators on the scheduling graph
static MSchedGraphNode& getSecond(std::pair<const MachineInstr* const,
- MSchedGraphNode*> &Pair) {
+ MSchedGraphNode*> &Pair) {
return *Pair.second;
}
@@ -338,7 +338,7 @@
return N->succ_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
+ MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
typedef mapped_iterator<MSchedGraph::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraph *G) {
@@ -383,7 +383,7 @@
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
+ MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
typedef mapped_iterator<MSchedGraph::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraph *G) {
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.3 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.4
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp:1.3 Mon Jul 11 17:46:18 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.cpp Wed Jul 27 00:53:44 2005
@@ -35,8 +35,8 @@
//MSchedGraphSBNode constructor
MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
- MSchedGraphSB *graph, unsigned idx,
- unsigned late, bool isBranch)
+ MSchedGraphSB *graph, unsigned idx,
+ unsigned late, bool isBranch)
: Inst(inst), Parent(graph), index(idx), latency(late),
isBranchInstr(isBranch) {
@@ -46,9 +46,9 @@
//MSchedGraphSBNode constructor
MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
- std::vector<const MachineInstr*> &other,
- MSchedGraphSB *graph, unsigned idx,
- unsigned late, bool isPNode)
+ std::vector<const MachineInstr*> &other,
+ MSchedGraphSB *graph, unsigned idx,
+ unsigned late, bool isPNode)
: Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) {
@@ -95,7 +95,7 @@
//Get the iteration difference for the edge from this node to its successor
unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) {
for(std::vector<MSchedGraphSBEdge>::iterator I = Successors.begin(),
- E = Successors.end();
+ E = Successors.end();
I != E; ++I) {
if(I->getDest() == succ)
return I->getIteDiff();
@@ -109,7 +109,7 @@
//return the edge the corresponds to this in edge
int count = 0;
for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
- E = pred->succ_end();
+ E = pred->succ_end();
I != E; ++I) {
if(*I == this)
return count;
@@ -130,7 +130,7 @@
//Dtermine if pred is a predecessor of this node
bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) {
if(std::find( Predecessors.begin(), Predecessors.end(),
- pred) != Predecessors.end())
+ pred) != Predecessors.end())
return true;
else
return false;
@@ -138,11 +138,11 @@
//Add a node to the graph
void MSchedGraphSB::addNode(const MachineInstr* MI,
- MSchedGraphSBNode *node) {
+ MSchedGraphSBNode *node) {
//Make sure node does not already exist
assert(GraphMap.find(MI) == GraphMap.end()
- && "New MSchedGraphSBNode already exists for this instruction");
+ && "New MSchedGraphSBNode already exists for this instruction");
GraphMap[MI] = node;
}
@@ -168,10 +168,10 @@
//is a special case in Modulo Scheduling. We only want to deal with
//the body of the loop.
MSchedGraphSB::MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm)
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm)
: BBs(bbs), Target(targ) {
//Make sure there is at least one BB and it is not null,
@@ -207,11 +207,11 @@
assert(cond && "Condition must not be null!");
if(Instruction *I = dyn_cast<Instruction>(cond)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
- if(tempMvec.size() > 0) {
- DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
- instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+ if(tempMvec.size() > 0) {
+ DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
+ instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
+ }
}
}
@@ -223,15 +223,15 @@
for (unsigned j = 0; j < tempMvec.size(); j++) {
MachineInstr *mi = tempMvec[j];
if(MTI->isNop(mi->getOpcode()))
- continue;
+ continue;
if(!instr) {
- instr = mi;
- DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
+ instr = mi;
+ DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
}
else {
- DEBUG(std::cerr << *mi << "\n");;
- otherInstrs.push_back(mi);
+ DEBUG(std::cerr << *mi << "\n");;
+ otherInstrs.push_back(mi);
}
}
@@ -245,22 +245,22 @@
for(MachineBasicBlock::iterator I = mb->begin(), E = mb->end(); I != E; ++I) {
MachineInstr *instr = I;
if(MTI->isNop(instr->getOpcode()) || MTI->isBranch(instr->getOpcode()))
- continue;
+ continue;
if(node->getInst() == instr)
- continue;
+ continue;
for(unsigned i=0; i < instr->getNumOperands(); ++i) {
- MachineOperand &mOp = instr->getOperand(i);
- if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
- Value *val = mOp.getVRegValue();
- //Check if there is a use not in the trace
- for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
- if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
- if(llvmBBs.count(Inst->getParent()))
- liveOutsideTrace[node].insert(instr);
- }
- }
- }
+ MachineOperand &mOp = instr->getOperand(i);
+ if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
+ Value *val = mOp.getVRegValue();
+ //Check if there is a use not in the trace
+ for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
+ if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
+ if(llvmBBs.count(Inst->getParent()))
+ liveOutsideTrace[node].insert(instr);
+ }
+ }
+ }
}
}
@@ -275,7 +275,7 @@
//Copies the graph and keeps a map from old to new nodes
MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G,
- std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes)
+ std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes)
: Target(G.Target) {
BBs = G.BBs;
@@ -283,7 +283,7 @@
std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> oldToNew;
//Copy all nodes
for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(),
- NE = G.GraphMap.end(); N != NE; ++N) {
+ NE = G.GraphMap.end(); N != NE; ++N) {
MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second));
oldToNew[&*(N->second)] = newNode;
@@ -381,9 +381,9 @@
//Add edges between the nodes
void MSchedGraphSB::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm,
- std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm,
+ std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
//Get Machine target information for calculating latency
@@ -401,19 +401,19 @@
for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
- BE = BBs.end(); B != BE; ++B) {
+ BE = BBs.end(); B != BE; ++B) {
const MachineBasicBlock *BB = *B;
//Loop over instructions in MBB and add nodes and edges
for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
- MI != e; ++MI) {
+ MI != e; ++MI) {
//Ignore indvar instructions
if(ignoreInstrs.count(MI)) {
- ++index;
- continue;
+ ++index;
+ continue;
}
//Get each instruction of machine basic block, get the delay
@@ -429,7 +429,7 @@
//Create new node for this machine instruction and add to the graph.
//Create only if not a nop
if(MTI->isNop(opCode))
- continue;
+ continue;
//Sparc BE does not use PHI opcode, so assert on this case
assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
@@ -438,106 +438,106 @@
//Skip branches
if(MTI->isBranch(opCode))
- continue;
+ continue;
//Node is created and added to the graph automatically
MSchedGraphSBNode *node = 0;
if(!GraphMap.count(MI)){
- node = new MSchedGraphSBNode(MI, this, index, delay);
- DEBUG(std::cerr << "Created Node: " << *node << "\n");
+ node = new MSchedGraphSBNode(MI, this, index, delay);
+ DEBUG(std::cerr << "Created Node: " << *node << "\n");
}
else {
- node = GraphMap[MI];
- if(node->isPredicate()) {
- //Create edge between this node and last pred, then switch to new pred
- if(lastPred) {
- lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
- MSchedGraphSBEdge::NonDataDep, 0);
-
- if(liveOutsideTrace.count(lastPred)) {
- for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
- lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
- MSchedGraphSBEdge::NonDataDep, 1);
- }
-
- }
-
- lastPred = node;
- }
+ node = GraphMap[MI];
+ if(node->isPredicate()) {
+ //Create edge between this node and last pred, then switch to new pred
+ if(lastPred) {
+ lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
+ MSchedGraphSBEdge::NonDataDep, 0);
+
+ if(liveOutsideTrace.count(lastPred)) {
+ for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
+ lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
+ MSchedGraphSBEdge::NonDataDep, 1);
+ }
+
+ }
+
+ lastPred = node;
+ }
}
//Add dependencies to instructions that cause exceptions
if(lastPred)
- lastPred->print(std::cerr);
+ lastPred->print(std::cerr);
if(!node->isPredicate() && instrCauseException(opCode)) {
- if(lastPred) {
- lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
- MSchedGraphSBEdge::NonDataDep, 0);
- }
+ if(lastPred) {
+ lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
+ MSchedGraphSBEdge::NonDataDep, 0);
+ }
}
//Check OpCode to keep track of memory operations to add memory
//dependencies later.
if(MTI->isLoad(opCode) || MTI->isStore(opCode))
- memInstructions.push_back(node);
+ memInstructions.push_back(node);
//Loop over all operands, and put them into the register number to
//graph node map for determining dependencies
//If an operands is a use/def, we have an anti dependence to itself
for(unsigned i=0; i < MI->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = MI->getOperand(i);
-
- //Check if it has an allocated register
- if(mOp.hasAllocatedReg()) {
- int regNum = mOp.getReg();
-
- if(regNum != SparcV9::g0) {
- //Put into our map
- regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
- }
- continue;
- }
-
-
- //Add virtual registers dependencies
- //Check if any exist in the value map already and create dependencies
- //between them.
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) {
-
- //Make sure virtual register value is not null
- assert((mOp.getVRegValue() != NULL) && "Null value is defined");
-
- //Check if this is a read operation in a phi node, if so DO NOT PROCESS
- if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
- DEBUG(std::cerr << "Read Operation in a PHI node\n");
- continue;
- }
-
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
-
- //Add to value map
- V->second.push_back(std::make_pair(i,node));
- }
- //Otherwise put it in the map
- else
- //Put into value map
- valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = MI->getOperand(i);
+
+ //Check if it has an allocated register
+ if(mOp.hasAllocatedReg()) {
+ int regNum = mOp.getReg();
+
+ if(regNum != SparcV9::g0) {
+ //Put into our map
+ regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
+ }
+ continue;
+ }
+
+
+ //Add virtual registers dependencies
+ //Check if any exist in the value map already and create dependencies
+ //between them.
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) {
+
+ //Make sure virtual register value is not null
+ assert((mOp.getVRegValue() != NULL) && "Null value is defined");
+
+ //Check if this is a read operation in a phi node, if so DO NOT PROCESS
+ if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
+ DEBUG(std::cerr << "Read Operation in a PHI node\n");
+ continue;
+ }
+
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
+
+ //Add to value map
+ V->second.push_back(std::make_pair(i,node));
+ }
+ //Otherwise put it in the map
+ else
+ //Put into value map
+ valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
+ }
+ }
}
++index;
}
@@ -546,15 +546,15 @@
//phiInstr list to process
const BasicBlock *llvm_bb = BB->getBasicBlock();
for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
- I != E; ++I) {
+ I != E; ++I) {
if(const PHINode *PN = dyn_cast<PHINode>(I)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- if(!ignoreInstrs.count(tempMvec[j])) {
- DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
- phiInstrs.push_back((MachineInstr*) tempMvec[j]);
- }
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ if(!ignoreInstrs.count(tempMvec[j])) {
+ DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
+ phiInstrs.push_back((MachineInstr*) tempMvec[j]);
+ }
+ }
}
}
@@ -564,14 +564,14 @@
//Finally deal with PHI Nodes and Value*
for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
- E = phiInstrs.end(); I != E; ++I) {
+ E = phiInstrs.end(); I != E; ++I) {
//Get Node for this instruction
std::map<const MachineInstr*, MSchedGraphSBNode*>::iterator X;
X = find(*I);
if(X == GraphMap.end())
- continue;
+ continue;
MSchedGraphSBNode *node = X->second;
@@ -579,38 +579,38 @@
//Loop over operands for this instruction and add value edges
for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = (*I)->getOperand(i);
- if((mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
-
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
- phiInstrs, 1);
- }
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = (*I)->getOperand(i);
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
+
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
+ phiInstrs, 1);
+ }
+ }
+ }
}
}
}
}
//Add dependencies for Value*s
void MSchedGraphSB::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphSBNode *destNode, bool nodeIsUse,
- bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
+ MSchedGraphSBNode *destNode, bool nodeIsUse,
+ bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
- E = NodesInMap.end(); I != E; ++I) {
+ E = NodesInMap.end(); I != E; ++I) {
//Get node in vectors machine operand that is the same value as node
MSchedGraphSBNode *srcNode = I->second;
@@ -618,26 +618,26 @@
if(diff > 0)
if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
- continue;
+ continue;
//Node is a Def, so add output dep.
if(nodeIsDef) {
if(mOp.isUse()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
- srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
- MSchedGraphSBEdge::AntiDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ MSchedGraphSBEdge::AntiDep, diff);
}
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
- srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
- MSchedGraphSBEdge::OutputDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ MSchedGraphSBEdge::OutputDep, diff);
}
}
if(nodeIsUse) {
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
- srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
- MSchedGraphSBEdge::TrueDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ MSchedGraphSBEdge::TrueDep, diff);
}
}
}
@@ -675,71 +675,71 @@
//Look at all instructions after this in execution order
for(unsigned j=i+1; j < Nodes.size(); ++j) {
-
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep);
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep);
+
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::TrueDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::TrueDep);
+ }
}
//Look at all the instructions before this one since machine registers
//could live across iterations.
for(unsigned j = 0; j < i; ++j) {
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep, 1);
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep, 1);
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep, 1);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep, 1);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep, 1);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep, 1);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep, 1);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::TrueDep,1 );
- }
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep, 1);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::TrueDep,1 );
+ }
+
}
@@ -752,8 +752,8 @@
//Add edges between all loads and stores
//Can be less strict with alias analysis and data dependence analysis.
void MSchedGraphSB::addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Target machine instruction info
const TargetInstrInfo *TMI = Target.getInstrInfo();
@@ -773,7 +773,7 @@
//No self loops
if(destIndex == srcIndex)
- continue;
+ continue;
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
@@ -783,7 +783,7 @@
//Assuming instructions without corresponding llvm instructions
//are from constant pools.
if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
- continue;
+ continue;
bool useDepAnalyzer = true;
@@ -792,78 +792,78 @@
Instruction *srcLLVM = machineTollvm[srcInst];
Instruction *destLLVM = machineTollvm[destInst];
if(!isa<LoadInst>(srcLLVM)
- && !isa<StoreInst>(srcLLVM)) {
- if(isa<BinaryOperator>(srcLLVM)) {
- if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(srcLLVM)) {
+ if(isa<BinaryOperator>(srcLLVM)) {
+ if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
if(!isa<LoadInst>(destLLVM)
- && !isa<StoreInst>(destLLVM)) {
- if(isa<BinaryOperator>(destLLVM)) {
- if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(destLLVM)) {
+ if(isa<BinaryOperator>(destLLVM)) {
+ if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
//Use dep analysis when we have corresponding llvm loads/stores
if(useDepAnalyzer) {
- bool srcBeforeDest = true;
- if(destIndex < srcIndex)
- srcBeforeDest = false;
-
- DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
- machineTollvm[destInst],
- srcBeforeDest);
-
- for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
- de = dr.dependences.end(); d != de; ++d) {
- //Add edge from load to store
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- d->getDepType(), d->getIteDiff());
-
- }
+ bool srcBeforeDest = true;
+ if(destIndex < srcIndex)
+ srcBeforeDest = false;
+
+ DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
+ machineTollvm[destInst],
+ srcBeforeDest);
+
+ for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
+ de = dr.dependences.end(); d != de; ++d) {
+ //Add edge from load to store
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ d->getDepType(), d->getIteDiff());
+
+ }
}
//Otherwise, we can not do any further analysis and must make a dependence
else {
-
- //Get the machine opCode to determine type of memory instruction
- MachineOpCode destNodeOpCode = destInst->getOpcode();
-
- //Get the Value* that we are reading from the load, always the first op
- const MachineOperand &mOp = srcInst->getOperand(0);
- const MachineOperand &mOp2 = destInst->getOperand(0);
-
- if(mOp.hasAllocatedReg())
- if(mOp.getReg() == SparcV9::g0)
- continue;
- if(mOp2.hasAllocatedReg())
- if(mOp2.getReg() == SparcV9::g0)
- continue;
-
- DEBUG(std::cerr << "Adding dependence for machine instructions\n");
- //Load-Store deps
- if(TMI->isLoad(srcNodeOpCode)) {
-
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- MSchedGraphSBEdge::AntiDep, 0);
- }
- else if(TMI->isStore(srcNodeOpCode)) {
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- MSchedGraphSBEdge::OutputDep, 0);
-
- else
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- MSchedGraphSBEdge::TrueDep, 0);
- }
+
+ //Get the machine opCode to determine type of memory instruction
+ MachineOpCode destNodeOpCode = destInst->getOpcode();
+
+ //Get the Value* that we are reading from the load, always the first op
+ const MachineOperand &mOp = srcInst->getOperand(0);
+ const MachineOperand &mOp2 = destInst->getOperand(0);
+
+ if(mOp.hasAllocatedReg())
+ if(mOp.getReg() == SparcV9::g0)
+ continue;
+ if(mOp2.hasAllocatedReg())
+ if(mOp2.getReg() == SparcV9::g0)
+ continue;
+
+ DEBUG(std::cerr << "Adding dependence for machine instructions\n");
+ //Load-Store deps
+ if(TMI->isLoad(srcNodeOpCode)) {
+
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ MSchedGraphSBEdge::AntiDep, 0);
+ }
+ else if(TMI->isStore(srcNodeOpCode)) {
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ MSchedGraphSBEdge::OutputDep, 0);
+
+ else
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ MSchedGraphSBEdge::TrueDep, 0);
+ }
}
}
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.1 llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.2
--- llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h:1.1 Thu Jun 16 23:16:14 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/MSchedGraphSB.h Wed Jul 27 00:53:44 2005
@@ -56,7 +56,7 @@
private:
friend class MSchedGraphSBNode;
MSchedGraphSBEdge(MSchedGraphSBNode *destination, MSchedGraphSBEdgeType type,
- unsigned deptype, unsigned diff)
+ unsigned deptype, unsigned diff)
: dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {}
MSchedGraphSBNode *dest;
@@ -84,10 +84,10 @@
public:
MSchedGraphSBNode(const MachineInstr* inst, MSchedGraphSB *graph,
- unsigned index, unsigned late=0, bool isBranch=false);
- MSchedGraphSBNode(const MachineInstr* inst, std::vector<const MachineInstr*> &other,
- MSchedGraphSB *graph,
- unsigned index, unsigned late=0, bool isPNode=true);
+ unsigned index, unsigned late=0, bool isBranch=false);
+ MSchedGraphSBNode(const MachineInstr* inst, std::vector<const MachineInstr*> &other,
+ MSchedGraphSB *graph,
+ unsigned index, unsigned late=0, bool isPNode=true);
MSchedGraphSBNode(const MSchedGraphSBNode &N);
//Iterators - Predecessor and Succussor
@@ -101,12 +101,12 @@
pred_const_iterator pred_end() const { return Predecessors.end(); }
typedef MSchedGraphSBNodeIterator<std::vector<MSchedGraphSBEdge>::const_iterator,
- const MSchedGraphSBNode> succ_const_iterator;
+ const MSchedGraphSBNode> succ_const_iterator;
succ_const_iterator succ_begin() const;
succ_const_iterator succ_end() const;
typedef MSchedGraphSBNodeIterator<std::vector<MSchedGraphSBEdge>::iterator,
- MSchedGraphSBNode> succ_iterator;
+ MSchedGraphSBNode> succ_iterator;
succ_iterator succ_begin();
succ_iterator succ_end();
unsigned succ_size() { return Successors.size(); }
@@ -126,17 +126,17 @@
void deleteSuccessor(MSchedGraphSBNode *node) {
for (unsigned i = 0; i != Successors.size(); ++i)
- if (Successors[i].getDest() == node) {
- Successors.erase(Successors.begin()+i);
- node->Predecessors.erase(std::find(node->Predecessors.begin(),
- node->Predecessors.end(), this));
- --i; //Decrease index var since we deleted a node
- }
+ if (Successors[i].getDest() == node) {
+ Successors.erase(Successors.begin()+i);
+ node->Predecessors.erase(std::find(node->Predecessors.begin(),
+ node->Predecessors.end(), this));
+ --i; //Decrease index var since we deleted a node
+ }
}
void addOutEdge(MSchedGraphSBNode *destination,
- MSchedGraphSBEdge::MSchedGraphSBEdgeType type,
- unsigned deptype, unsigned diff=0) {
+ MSchedGraphSBEdge::MSchedGraphSBEdgeType type,
+ unsigned deptype, unsigned diff=0) {
Successors.push_back(MSchedGraphSBEdge(destination, type, deptype,diff));
destination->Predecessors.push_back(this);
}
@@ -215,7 +215,7 @@
// ostream << operator for MSGraphNode class
inline std::ostream &operator<<(std::ostream &os,
- const MSchedGraphSBNode &node) {
+ const MSchedGraphSBNode &node) {
node.print(os);
return os;
}
@@ -253,29 +253,29 @@
typedef std::pair<int, MSchedGraphSBNode*> OpIndexNodePair;
void buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm, std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace);
void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphSBNode *node,
- bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
+ MSchedGraphSBNode *node,
+ bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
void addMachRegEdges(std::map<int,
- std::vector<OpIndexNodePair> >& regNumtoNodeMap);
+ std::vector<OpIndexNodePair> >& regNumtoNodeMap);
void addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
-
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+
bool instrCauseException(MachineOpCode opCode);
public:
MSchedGraphSB(const MachineBasicBlock *bb, const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
//Copy constructor with maps to link old nodes to new nodes
MSchedGraphSB(const MSchedGraphSB &G, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
-
- MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm);
+
+ MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm);
//Print graph
void print(std::ostream &os) const;
@@ -311,7 +311,7 @@
// Provide specializations of GraphTraits to be able to use graph
// iterators on the scheduling graph
static MSchedGraphSBNode& getSecond(std::pair<const MachineInstr* const,
- MSchedGraphSBNode*> &Pair) {
+ MSchedGraphSBNode*> &Pair) {
return *Pair.second;
}
@@ -350,7 +350,7 @@
return N->succ_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraphSB *G) {
@@ -395,7 +395,7 @@
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraphSB *G) {
Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.50 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.51
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp:1.50 Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp Wed Jul 27 00:53:44 2005
@@ -100,34 +100,34 @@
static std::string getNodeLabel(MSchedGraphNode *Node, MSchedGraph *Graph) {
if (Node->getInst()) {
- std::stringstream ss;
- ss << *(Node->getInst());
- return ss.str(); //((MachineInstr*)Node->getInst());
+ std::stringstream ss;
+ ss << *(Node->getInst());
+ return ss.str(); //((MachineInstr*)Node->getInst());
}
else
- return "No Inst";
+ return "No Inst";
}
static std::string getEdgeSourceLabel(MSchedGraphNode *Node,
- MSchedGraphNode::succ_iterator I) {
+ MSchedGraphNode::succ_iterator I) {
//Label each edge with the type of dependence
std::string edgelabel = "";
switch (I.getEdge().getDepOrderType()) {
-
+
case MSchedGraphEdge::TrueDep:
- edgelabel = "True";
- break;
+ edgelabel = "True";
+ break;
case MSchedGraphEdge::AntiDep:
- edgelabel = "Anti";
- break;
-
+ edgelabel = "Anti";
+ break;
+
case MSchedGraphEdge::OutputDep:
- edgelabel = "Output";
- break;
-
+ edgelabel = "Output";
+ break;
+
default:
- edgelabel = "Unknown";
- break;
+ edgelabel = "Unknown";
+ break;
}
//FIXME
@@ -173,11 +173,11 @@
for (MachineFunction::iterator BI = MF.begin(); BI != MF.end(); ++BI)
if(MachineBBisValid(BI)) {
if(BI->size() < 100) {
- Worklist.push_back(&*BI);
- ++ValidLoops;
+ Worklist.push_back(&*BI);
+ ++ValidLoops;
}
else
- ++JumboBB;
+ ++JumboBB;
}
@@ -187,7 +187,7 @@
//Iterate over the worklist and perform scheduling
for(std::vector<MachineBasicBlock*>::iterator BI = Worklist.begin(),
- BE = Worklist.end(); BI != BE; ++BI) {
+ BE = Worklist.end(); BI != BE; ++BI) {
//Print out BB for debugging
DEBUG(std::cerr << "BB Size: " << (*BI)->size() << "\n");
@@ -236,41 +236,41 @@
//Dump node properties if in debug mode
DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
- << " Height: " << I->second.height << "\n";
- });
+ E = nodeToAttributesMap.end(); I !=E; ++I) {
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ << " Height: " << I->second.height << "\n";
+ });
//Calculate Node Properties
calculateNodeAttributes(MSG, ResMII);
//Dump node properties if in debug mode
DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
- << " Height: " << I->second.height << "\n";
- });
+ E = nodeToAttributesMap.end(); I !=E; ++I) {
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ << " Height: " << I->second.height << "\n";
+ });
//Put nodes in order to schedule them
computePartialOrder();
//Dump out partial order
DEBUG(for(std::vector<std::set<MSchedGraphNode*> >::iterator I = partialOrder.begin(),
- E = partialOrder.end(); I !=E; ++I) {
- std::cerr << "Start set in PO\n";
- for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
- std::cerr << "PO:" << **J << "\n";
- });
+ E = partialOrder.end(); I !=E; ++I) {
+ std::cerr << "Start set in PO\n";
+ for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+ std::cerr << "PO:" << **J << "\n";
+ });
//Place nodes in final order
orderNodes();
//Dump out order of nodes
DEBUG(for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) {
- std::cerr << "FO:" << **I << "\n";
- });
+ std::cerr << "FO:" << **I << "\n";
+ });
//Finally schedule nodes
bool haveSched = computeSchedule(*BI, MSG);
@@ -288,7 +288,7 @@
IISum += mII;
if(schedule.getMaxStage() == 0)
- ++SameStage;
+ ++SameStage;
}
else {
++NoSched;
@@ -323,20 +323,20 @@
for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) {
const MachineOperand &mOp = I->getOperand(opNum);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- //assert if this is the second def we have seen
- //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
- //assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
- if(defMap.count(mOp.getVRegValue()))
- return false;
+ //assert if this is the second def we have seen
+ //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
+ //assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
+ if(defMap.count(mOp.getVRegValue()))
+ return false;
- defMap[mOp.getVRegValue()] = &*I;
+ defMap[mOp.getVRegValue()] = &*I;
}
//See if we can use this Value* as our defaultInst
if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
- Value *V = mOp.getVRegValue();
- if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
- defaultInst = (Instruction*) V;
+ Value *V = mOp.getVRegValue();
+ if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
+ defaultInst = (Instruction*) V;
}
}
}
@@ -357,7 +357,7 @@
//Check first if its a valid loop
for(succ_const_iterator I = succ_begin(BI->getBasicBlock()),
- E = succ_end(BI->getBasicBlock()); I != E; ++I) {
+ E = succ_end(BI->getBasicBlock()); I != E; ++I) {
if (*I == BI->getBasicBlock()) // has single block loop
isLoop = true;
}
@@ -437,8 +437,8 @@
if(Instruction *I = dyn_cast<Instruction>(cond))
if(I->getParent() == BB) {
if (!assocIndVar(I, indVar, stack, BB)) {
- ++InvalidLoops;
- return false;
+ ++InvalidLoops;
+ return false;
}
}
else {
@@ -455,8 +455,8 @@
//Dump out instructions associate with indvar for debug reasons
DEBUG(for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
- std::cerr << **N << "\n";
- });
+ std::cerr << **N << "\n";
+ });
//Create map of machine instr to llvm instr
std::map<MachineInstr*, Instruction*> mllvm;
@@ -480,9 +480,9 @@
for (unsigned j = 0; j < tempMvec.size(); j++) {
MachineOpCode OC = (tempMvec[j])->getOpcode();
if(TMI->isNop(OC))
- continue;
+ continue;
if(!indexMap.count(tempMvec[j]))
- continue;
+ continue;
mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
}
@@ -499,7 +499,7 @@
}
bool ModuloSchedulingPass::assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack, BasicBlock *BB) {
+ std::vector<Instruction*> &stack, BasicBlock *BB) {
stack.push_back(I);
@@ -510,21 +510,21 @@
if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
if (CI->equalsInt(1)) {
- //We have found the indvar, so add the stack, and inc instruction to the set
- indVar.insert(stack.begin(), stack.end());
- indVar.insert(Inc);
- stack.pop_back();
- return true;
- }
+ //We have found the indvar, so add the stack, and inc instruction to the set
+ indVar.insert(stack.begin(), stack.end());
+ indVar.insert(Inc);
+ stack.pop_back();
+ return true;
+ }
return false;
}
else {
//Loop over each of the instructions operands, check if they are an instruction and in this BB
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
if(Instruction *N = dyn_cast<Instruction>(I->getOperand(i))) {
- if(N->getParent() == BB)
- if(!assocIndVar(N, indVar, stack, BB))
- return false;
+ if(N->getParent() == BB)
+ if(!assocIndVar(N, indVar, stack, BB))
+ return false;
}
}
}
@@ -558,12 +558,12 @@
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i)
for(unsigned j=0; j < resources[i].size(); ++j) {
- if(!resourceUsageCount.count(resources[i][j])) {
- resourceUsageCount[resources[i][j]] = 1;
- }
- else {
- resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
- }
+ if(!resourceUsageCount.count(resources[i][j])) {
+ resourceUsageCount[resources[i][j]] = 1;
+ }
+ else {
+ resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
+ }
}
}
@@ -638,7 +638,7 @@
//Assert if its already in the map
assert(nodeToAttributesMap.count(I->second) == 0 &&
- "Node attributes are already in the map");
+ "Node attributes are already in the map");
//Put into the map with default attribute values
nodeToAttributesMap[I->second] = MSNodeAttributes();
@@ -724,7 +724,7 @@
int ModuloSchedulingPass::calculateALAP(MSchedGraphNode *node, int MII,
- int maxASAP, MSchedGraphNode *srcNode) {
+ int maxASAP, MSchedGraphNode *srcNode) {
DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n");
@@ -745,28 +745,28 @@
//Iterate over all of the predecessors and fine max
for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
//Only process if we are not ignoring the edge
if(!ignoreEdge(node, *P)) {
- processedOneEdge = true;
- int succALAP = -1;
- succALAP = calculateALAP(*P, MII, maxASAP, node);
-
- assert(succALAP != -1 && "Successors ALAP should have been caclulated");
-
- int iteDiff = P.getEdge().getIteDiff();
-
- int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
-
- DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
+ processedOneEdge = true;
+ int succALAP = -1;
+ succALAP = calculateALAP(*P, MII, maxASAP, node);
+
+ assert(succALAP != -1 && "Successors ALAP should have been caclulated");
+
+ int iteDiff = P.getEdge().getIteDiff();
+
+ int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
+
+ DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
- minSuccValue = std::min(minSuccValue, currentSuccValue);
+ minSuccValue = std::min(minSuccValue, currentSuccValue);
}
}
if(processedOneEdge)
- attributes.ALAP = minSuccValue;
+ attributes.ALAP = minSuccValue;
else
attributes.ALAP = maxASAP;
@@ -786,7 +786,7 @@
int maxASAP = 0;
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I)
+ E = nodeToAttributesMap.end(); I != E; ++I)
maxASAP = std::max(maxASAP, I->second.ASAP);
return maxASAP;
}
@@ -803,7 +803,7 @@
//Iterate over all of the predecessors and find max
for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
if(!ignoreEdge(node, *P)) {
@@ -822,7 +822,7 @@
int ModuloSchedulingPass::calculateDepth(MSchedGraphNode *node,
- MSchedGraphNode *destNode) {
+ MSchedGraphNode *destNode) {
MSNodeAttributes &attributes = nodeToAttributesMap.find(node)->second;
@@ -865,16 +865,16 @@
if(R->second.size() == recurrence.size()) {
for(std::vector<MSchedGraphNode*>::const_iterator node = R->second.begin(), end = R->second.end(); node != end; ++node) {
- if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) {
- all_same = all_same && false;
- break;
- }
- else
- all_same = all_same && true;
+ if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) {
+ all_same = all_same && false;
+ break;
+ }
+ else
+ all_same = all_same && true;
}
if(all_same) {
- same = true;
- break;
+ same = true;
+ break;
}
}
}
@@ -888,12 +888,12 @@
//DEBUG(std::cerr << "NOT A BACKEDGE\n");
//find actual backedge HACK HACK
for(unsigned i=0; i< recurrence.size()-1; ++i) {
- if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) {
- srcBENode = recurrence[i];
- destBENode = recurrence[i+1];
- break;
- }
-
+ if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) {
+ srcBENode = recurrence[i];
+ destBENode = recurrence[i+1];
+ break;
+ }
+
}
}
@@ -907,7 +907,7 @@
int CircCount;
void ModuloSchedulingPass::unblock(MSchedGraphNode *u, std::set<MSchedGraphNode*> &blocked,
- std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B) {
+ std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B) {
//Unblock u
DEBUG(std::cerr << "Unblocking: " << *u << "\n");
@@ -926,9 +926,9 @@
}
bool ModuloSchedulingPass::circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
- std::set<MSchedGraphNode*> &blocked, std::vector<MSchedGraphNode*> &SCC,
- MSchedGraphNode *s, std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B,
- int II, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes) {
+ std::set<MSchedGraphNode*> &blocked, std::vector<MSchedGraphNode*> &SCC,
+ MSchedGraphNode *s, std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B,
+ int II, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes) {
bool f = false;
DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n");
@@ -955,7 +955,7 @@
}
else if(!blocked.count(*I)) {
if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes))
- f = true;
+ f = true;
}
else
DEBUG(std::cerr << "Blocked: " << **I << "\n");
@@ -982,7 +982,7 @@
std::vector<MSchedGraphNode*> recc;
//Dump recurrence for now
DEBUG(std::cerr << "Starting Recc\n");
-
+
int totalDelay = 0;
int totalDistance = 0;
MSchedGraphNode *lastN = 0;
@@ -998,8 +998,8 @@
totalDistance += iteDiff;
if(iteDiff > 0) {
- start = lastN;
- end = *N;
+ start = lastN;
+ end = *N;
}
}
//Get the original node
@@ -1015,7 +1015,7 @@
DEBUG(std::cerr << "End Recc\n");
CircCount++;
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
@@ -1031,7 +1031,7 @@
int value = totalDelay-(RecMII * totalDistance);
int lastII = II;
while(value < 0) {
-
+
lastII = RecMII;
RecMII--;
value = totalDelay-(RecMII * totalDistance);
@@ -1057,13 +1057,13 @@
for(unsigned i = 0; i < (*N)->succ_size(); ++i) {
MSchedGraphEdge *edge = (*N)->getSuccessor(i);
if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) {
- totalDistance += edge->getIteDiff();
- if(edge->getIteDiff() > 0)
- if(!start && !end) {
- start = *N;
- end = edge->getDest();
- }
-
+ totalDistance += edge->getIteDiff();
+ if(edge->getIteDiff() > 0)
+ if(!start && !end) {
+ start = *N;
+ end = edge->getDest();
+ }
+
}
}
@@ -1079,7 +1079,7 @@
assert( (start && end) && "Must have start and end node to ignore edge for SCC");
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
@@ -1135,76 +1135,76 @@
//Find scc with the least vertex
for (MSchedGraph::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI)
if (Visited.insert(GI->second).second) {
- for (scc_iterator<MSchedGraphNode*> SCCI = scc_begin(GI->second),
- E = scc_end(GI->second); SCCI != E; ++SCCI) {
- std::vector<MSchedGraphNode*> &nextSCC = *SCCI;
-
- if (Visited.insert(nextSCC[0]).second) {
- Visited.insert(nextSCC.begin()+1, nextSCC.end());
-
- if(nextSCC.size() > 1) {
- std::cerr << "SCC size: " << nextSCC.size() << "\n";
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- //Loop over successor and see if in scc, then count edge
- MSchedGraphNode *node = nextSCC[i];
- for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
- if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
- numEdges++;
- }
- }
- std::cerr << "Num Edges: " << numEdges << "\n";
- }
-
- //Ignore self loops
- if(nextSCC.size() > 1) {
-
- //Get least vertex in Vk
- if(!s) {
- s = nextSCC[0];
- Vk = nextSCC;
- }
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- if(nextSCC[i] < s) {
- s = nextSCC[i];
- Vk = nextSCC;
- }
- }
- }
- }
- }
+ for (scc_iterator<MSchedGraphNode*> SCCI = scc_begin(GI->second),
+ E = scc_end(GI->second); SCCI != E; ++SCCI) {
+ std::vector<MSchedGraphNode*> &nextSCC = *SCCI;
+
+ if (Visited.insert(nextSCC[0]).second) {
+ Visited.insert(nextSCC.begin()+1, nextSCC.end());
+
+ if(nextSCC.size() > 1) {
+ std::cerr << "SCC size: " << nextSCC.size() << "\n";
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ //Loop over successor and see if in scc, then count edge
+ MSchedGraphNode *node = nextSCC[i];
+ for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
+ if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
+ numEdges++;
+ }
+ }
+ std::cerr << "Num Edges: " << numEdges << "\n";
+ }
+
+ //Ignore self loops
+ if(nextSCC.size() > 1) {
+
+ //Get least vertex in Vk
+ if(!s) {
+ s = nextSCC[0];
+ Vk = nextSCC;
+ }
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ if(nextSCC[i] < s) {
+ s = nextSCC[i];
+ Vk = nextSCC;
+ }
+ }
+ }
+ }
+ }
}
//Process SCC
DEBUG(for(std::vector<MSchedGraphNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) { std::cerr << *((*N)->getInst()); });
+ N != NE; ++N) { std::cerr << *((*N)->getInst()); });
//Iterate over all nodes in this scc
for(std::vector<MSchedGraphNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) {
+ N != NE; ++N) {
blocked.erase(*N);
B[*N].clear();
}
if(Vk.size() > 1) {
if(numEdges < 98)
- circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+ circuit(s, stack, blocked, Vk, s, B, II, newNodes);
else
- addSCC(Vk, newNodes);
+ addSCC(Vk, newNodes);
//Delete nodes from the graph
//Find all nodes up to s and delete them
std::vector<MSchedGraphNode*> nodesToRemove;
nodesToRemove.push_back(s);
for(MSchedGraph::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) {
- if(N->second < s )
- nodesToRemove.push_back(N->second);
+ if(N->second < s )
+ nodesToRemove.push_back(N->second);
}
for(std::vector<MSchedGraphNode*>::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) {
- DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
- MSG->deleteNode(*N);
+ DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
+ MSG->deleteNode(*N);
}
}
else
@@ -1215,8 +1215,8 @@
void ModuloSchedulingPass::findAllReccurrences(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &visitedNodes,
- int II) {
+ std::vector<MSchedGraphNode*> &visitedNodes,
+ int II) {
if(std::find(visitedNodes.begin(), visitedNodes.end(), node) != visitedNodes.end()) {
@@ -1232,22 +1232,22 @@
for(std::vector<MSchedGraphNode*>::iterator I = visitedNodes.begin(), E = visitedNodes.end();
- I !=E; ++I) {
+ I !=E; ++I) {
if(*I == node)
- first = false;
+ first = false;
if(first)
- continue;
+ continue;
delay = delay + (*I)->getLatency();
if(*I != node) {
- int diff = (*I)->getInEdge(last).getIteDiff();
- distance += diff;
- if(diff > 0) {
- srcBackEdge = last;
- destBackEdge = *I;
- }
+ int diff = (*I)->getInEdge(last).getIteDiff();
+ distance += diff;
+ if(diff > 0) {
+ srcBackEdge = last;
+ destBackEdge = *I;
+ }
}
recurrence.push_back(*I);
@@ -1289,9 +1289,9 @@
}
void ModuloSchedulingPass::searchPath(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &nodesToAdd,
- std::set<MSchedGraphNode*> &new_reccurrence) {
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &nodesToAdd,
+ std::set<MSchedGraphNode*> &new_reccurrence) {
//Push node onto the path
path.push_back(node);
@@ -1314,11 +1314,11 @@
//final vector
bool found = false;
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(*S)) {
- found = true;
- break;
+ found = true;
+ break;
}
}
@@ -1333,9 +1333,9 @@
}
void ModuloSchedulingPass::pathToRecc(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &poSet,
- std::set<MSchedGraphNode*> &lastNodes) {
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &poSet,
+ std::set<MSchedGraphNode*> &lastNodes) {
//Push node onto the path
path.push_back(node);
@@ -1354,11 +1354,11 @@
DEBUG(std::cerr << "Found path to recc from no pred\n");
//Loop over path, if it exists in lastNodes, then add to poset, and remove from lastNodes
for(std::vector<MSchedGraphNode*>::iterator I = path.begin(), IE = path.end(); I != IE; ++I) {
- if(lastNodes.count(*I)) {
- DEBUG(std::cerr << "Inserting node into recc: " << **I << "\n");
- poSet.insert(*I);
- lastNodes.erase(*I);
- }
+ if(lastNodes.count(*I)) {
+ DEBUG(std::cerr << "Inserting node into recc: " << **I << "\n");
+ poSet.insert(*I);
+ lastNodes.erase(*I);
+ }
}
}
else
@@ -1387,28 +1387,28 @@
//along with any nodes that connect this recurrence to recurrences
//already in the partial order
for(std::set<std::pair<int, std::vector<MSchedGraphNode*> > >::reverse_iterator
- I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
+ I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
std::set<MSchedGraphNode*> new_recurrence;
//Loop through recurrence and remove any nodes already in the partial order
for(std::vector<MSchedGraphNode*>::const_iterator N = I->second.begin(),
- NE = I->second.end(); N != NE; ++N) {
+ NE = I->second.end(); N != NE; ++N) {
bool found = false;
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
}
//Check if its a branch, and remove to handle special
if(!found) {
- if((*N)->isBranch() && !(*N)->hasPredecessors()) {
- branches.push_back(*N);
- }
- else
- new_recurrence.insert(*N);
+ if((*N)->isBranch() && !(*N)->hasPredecessors()) {
+ branches.push_back(*N);
+ }
+ else
+ new_recurrence.insert(*N);
}
}
@@ -1426,21 +1426,21 @@
//Add nodes that connect this recurrence to recurrences in the partial path
for(std::set<MSchedGraphNode*>::iterator N = new_recurrence.begin(),
NE = new_recurrence.end(); N != NE; ++N)
- searchPath(*N, path, nodesToAdd, new_recurrence);
+ searchPath(*N, path, nodesToAdd, new_recurrence);
//Add nodes to this recurrence if they are not already in the partial order
for(std::set<MSchedGraphNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
- N != NE; ++N) {
- bool found = false;
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
- }
- if(!found) {
- assert("FOUND CONNECTOR");
- new_recurrence.insert(*N);
- }
+ N != NE; ++N) {
+ bool found = false;
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
+ }
+ if(!found) {
+ assert("FOUND CONNECTOR");
+ new_recurrence.insert(*N);
+ }
}
partialOrder.push_back(new_recurrence);
@@ -1448,11 +1448,11 @@
//Dump out partial order
DEBUG(for(std::vector<std::set<MSchedGraphNode*> >::iterator I = partialOrder.begin(),
- E = partialOrder.end(); I !=E; ++I) {
- std::cerr << "Start set in PO\n";
- for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
- std::cerr << "PO:" << **J << "\n";
- });
+ E = partialOrder.end(); I !=E; ++I) {
+ std::cerr << "Start set in PO\n";
+ for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+ std::cerr << "PO:" << **J << "\n";
+ });
}
}
@@ -1462,15 +1462,15 @@
std::set<MSchedGraphNode*> lastNodes;
std::set<MSchedGraphNode*> noPredNodes;
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I) {
+ E = nodeToAttributesMap.end(); I != E; ++I) {
bool found = false;
//Check if its already in our partial order, if not add it to the final vector
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(I->first))
- found = true;
+ found = true;
}
if(!found)
lastNodes.insert(I->first);
@@ -1482,7 +1482,7 @@
N != NE; ++N) {
DEBUG(std::cerr << "No Pred Path from: " << **N << "\n");
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
std::vector<MSchedGraphNode*> path;
pathToRecc(*N, path, *PO, lastNodes);
}
@@ -1495,7 +1495,7 @@
std::set<MSchedGraphNode*> ccSet;
connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes);
if(ccSet.size() > 0)
- partialOrder.push_back(ccSet);
+ partialOrder.push_back(ccSet);
}
@@ -1525,15 +1525,15 @@
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
- E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(*P,FinalNodeOrder[j]))
- continue;
-
+ continue;
+
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
@@ -1546,15 +1546,15 @@
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
- E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(FinalNodeOrder[j],*P))
- continue;
+ continue;
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
@@ -1604,28 +1604,28 @@
//sort top-down
if(IntersectCurrent.size() != 0) {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
- order = TOP_DOWN;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
+ order = TOP_DOWN;
}
else {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
- //Find node with max ASAP in current Set
- MSchedGraphNode *node;
- int maxASAP = 0;
- DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
- for(std::set<MSchedGraphNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
- //Get node attributes
- MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
- //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
-
- if(maxASAP <= nodeAttr.ASAP) {
- maxASAP = nodeAttr.ASAP;
- node = *J;
- }
- }
- assert(node != 0 && "In node ordering node should not be null");
- IntersectCurrent.insert(node);
- order = BOTTOM_UP;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
+ //Find node with max ASAP in current Set
+ MSchedGraphNode *node;
+ int maxASAP = 0;
+ DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
+ for(std::set<MSchedGraphNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
+ //Get node attributes
+ MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
+ //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
+
+ if(maxASAP <= nodeAttr.ASAP) {
+ maxASAP = nodeAttr.ASAP;
+ node = *J;
+ }
+ }
+ assert(node != 0 && "In node ordering node should not be null");
+ IntersectCurrent.insert(node);
+ order = BOTTOM_UP;
}
}
@@ -1633,138 +1633,138 @@
while(IntersectCurrent.size() > 0) {
if(order == TOP_DOWN) {
- DEBUG(std::cerr << "Order is TOP DOWN\n");
+ DEBUG(std::cerr << "Order is TOP DOWN\n");
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
-
- int MOB = 0;
- int height = 0;
- MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin());
-
- //Find node in intersection with highest heigh and lowest MOB
- for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
-
- //Get current nodes properties
- MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(height < nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- else if(height == nodeAttr.height) {
- if(MOB > nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
- //Append our node with greatest height to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
- FinalNodeOrder.push_back(highestHeightNode);
- }
-
- //Remove V from IntersectOrder
- IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
- IntersectCurrent.end(), highestHeightNode));
-
-
- //Intersect V's successors with CurrentSet
- for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(),
- E = highestHeightNode->succ_end(); P != E; ++P) {
- //if(lower_bound(CurrentSet->begin(),
- // CurrentSet->end(), *P) != CurrentSet->end()) {
- if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
- if(ignoreEdge(highestHeightNode, *P))
- continue;
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
- } //End while loop over Intersect Size
-
- //Change direction
- order = BOTTOM_UP;
-
- //Reset Intersect to reflect changes in OrderNodes
- IntersectCurrent.clear();
- predIntersect(*CurrentSet, IntersectCurrent);
-
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
+
+ int MOB = 0;
+ int height = 0;
+ MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin());
+
+ //Find node in intersection with highest heigh and lowest MOB
+ for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+
+ //Get current nodes properties
+ MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(height < nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ else if(height == nodeAttr.height) {
+ if(MOB > nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+ //Append our node with greatest height to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
+ FinalNodeOrder.push_back(highestHeightNode);
+ }
+
+ //Remove V from IntersectOrder
+ IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
+ IntersectCurrent.end(), highestHeightNode));
+
+
+ //Intersect V's successors with CurrentSet
+ for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(),
+ E = highestHeightNode->succ_end(); P != E; ++P) {
+ //if(lower_bound(CurrentSet->begin(),
+ // CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(ignoreEdge(highestHeightNode, *P))
+ continue;
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+ } //End while loop over Intersect Size
+
+ //Change direction
+ order = BOTTOM_UP;
+
+ //Reset Intersect to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ predIntersect(*CurrentSet, IntersectCurrent);
+
} //End If TOP_DOWN
-
- //Begin if BOTTOM_UP
+
+ //Begin if BOTTOM_UP
else {
- DEBUG(std::cerr << "Order is BOTTOM UP\n");
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
-
- //dump intersection
- DEBUG(dumpIntersection(IntersectCurrent));
- //Get node with highest depth, if a tie, use one with lowest
- //MOB
- int MOB = 0;
- int depth = 0;
- MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin());
-
- for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
- //Find node attribute in graph
- MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(depth < nodeAttr.depth) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- else if(depth == nodeAttr.depth) {
- if(MOB > nodeAttr.MOB) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
-
-
- //Append highest depth node to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
- FinalNodeOrder.push_back(highestDepthNode);
- }
- //Remove heightestDepthNode from IntersectOrder
- IntersectCurrent.erase(highestDepthNode);
-
-
- //Intersect heightDepthNode's pred with CurrentSet
- for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(),
- E = highestDepthNode->pred_end(); P != E; ++P) {
- if(CurrentSet->count(*P)) {
- if(ignoreEdge(*P, highestDepthNode))
- continue;
-
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
-
- } //End while loop over Intersect Size
-
- //Change order
- order = TOP_DOWN;
-
- //Reset IntersectCurrent to reflect changes in OrderNodes
- IntersectCurrent.clear();
- succIntersect(*CurrentSet, IntersectCurrent);
- } //End if BOTTOM_DOWN
-
+ DEBUG(std::cerr << "Order is BOTTOM UP\n");
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
+
+ //dump intersection
+ DEBUG(dumpIntersection(IntersectCurrent));
+ //Get node with highest depth, if a tie, use one with lowest
+ //MOB
+ int MOB = 0;
+ int depth = 0;
+ MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin());
+
+ for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+ //Find node attribute in graph
+ MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(depth < nodeAttr.depth) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ else if(depth == nodeAttr.depth) {
+ if(MOB > nodeAttr.MOB) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+
+
+ //Append highest depth node to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
+ FinalNodeOrder.push_back(highestDepthNode);
+ }
+ //Remove heightestDepthNode from IntersectOrder
+ IntersectCurrent.erase(highestDepthNode);
+
+
+ //Intersect heightDepthNode's pred with CurrentSet
+ for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(),
+ E = highestDepthNode->pred_end(); P != E; ++P) {
+ if(CurrentSet->count(*P)) {
+ if(ignoreEdge(*P, highestDepthNode))
+ continue;
+
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+
+ } //End while loop over Intersect Size
+
+ //Change order
+ order = TOP_DOWN;
+
+ //Reset IntersectCurrent to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ succIntersect(*CurrentSet, IntersectCurrent);
+ } //End if BOTTOM_DOWN
+
DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n");
}
//End Wrapping while loop
@@ -1802,7 +1802,7 @@
//Loop over the final node order and process each node
for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(),
- E = FinalNodeOrder.end(); I != E; ++I) {
+ E = FinalNodeOrder.end(); I != E; ++I) {
//CalculateEarly and Late start
bool initialLSVal = false;
@@ -1814,85 +1814,85 @@
bool sched;
if((*I)->isBranch())
- if((*I)->hasPredecessors())
- sched = true;
- else
- sched = false;
+ if((*I)->hasPredecessors())
+ sched = true;
+ else
+ sched = false;
else
- sched = true;
+ sched = true;
if(sched) {
- //Loop over nodes in the schedule and determine if they are predecessors
- //or successors of the node we are trying to schedule
- for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
- nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
-
- //For this cycle, get the vector of nodes schedule and loop over it
- for(std::vector<MSchedGraphNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
-
- if((*I)->isPredecessor(*schedNode)) {
- int diff = (*I)->getInEdge(*schedNode).getIteDiff();
- int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- if(initialESVal)
- EarlyStart = std::max(EarlyStart, ES_Temp);
- else {
- EarlyStart = ES_Temp;
- initialESVal = true;
- }
- hasPred = true;
- }
- if((*I)->isSuccessor(*schedNode)) {
- int diff = (*schedNode)->getInEdge(*I).getIteDiff();
- int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- if(initialLSVal)
- LateStart = std::min(LateStart, LS_Temp);
- else {
- LateStart = LS_Temp;
- initialLSVal = true;
- }
- hasSucc = true;
- }
- }
- }
+ //Loop over nodes in the schedule and determine if they are predecessors
+ //or successors of the node we are trying to schedule
+ for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
+ nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
+
+ //For this cycle, get the vector of nodes schedule and loop over it
+ for(std::vector<MSchedGraphNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
+
+ if((*I)->isPredecessor(*schedNode)) {
+ int diff = (*I)->getInEdge(*schedNode).getIteDiff();
+ int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+ if(initialESVal)
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ else {
+ EarlyStart = ES_Temp;
+ initialESVal = true;
+ }
+ hasPred = true;
+ }
+ if((*I)->isSuccessor(*schedNode)) {
+ int diff = (*schedNode)->getInEdge(*I).getIteDiff();
+ int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+ if(initialLSVal)
+ LateStart = std::min(LateStart, LS_Temp);
+ else {
+ LateStart = LS_Temp;
+ initialLSVal = true;
+ }
+ hasSucc = true;
+ }
+ }
+ }
}
else {
- branches.push_back(*I);
- continue;
+ branches.push_back(*I);
+ continue;
}
//Check if this node is a pred or succ to a branch, and restrict its placement
//even though the branch is not in the schedule
/*int count = branches.size();
for(std::vector<MSchedGraphNode*>::iterator B = branches.begin(), BE = branches.end();
- B != BE; ++B) {
- if((*I)->isPredecessor(*B)) {
- int diff = (*I)->getInEdge(*B).getIteDiff();
- int ES_Temp = (II+count-1) + (*B)->getLatency() - diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count)-1 << "\n");
- DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- EarlyStart = std::max(EarlyStart, ES_Temp);
- hasPred = true;
- }
-
- if((*I)->isSuccessor(*B)) {
- int diff = (*B)->getInEdge(*I).getIteDiff();
- int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count-1) << "\n");
- DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- LateStart = std::min(LateStart, LS_Temp);
- hasSucc = true;
- }
-
- count--;
+ B != BE; ++B) {
+ if((*I)->isPredecessor(*B)) {
+ int diff = (*I)->getInEdge(*B).getIteDiff();
+ int ES_Temp = (II+count-1) + (*B)->getLatency() - diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count)-1 << "\n");
+ DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ hasPred = true;
+ }
+
+ if((*I)->isSuccessor(*B)) {
+ int diff = (*B)->getInEdge(*I).getIteDiff();
+ int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count-1) << "\n");
+ DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+ LateStart = std::min(LateStart, LS_Temp);
+ hasSucc = true;
+ }
+
+ count--;
}*/
//Check if the node has no pred or successors and set Early Start to its ASAP
if(!hasSucc && !hasPred)
- EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
+ EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n");
DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n");
@@ -1900,25 +1900,25 @@
//Now, try to schedule this node depending upon its pred and successor in the schedule
//already
if(!hasSucc && hasPred)
- success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
+ success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
else if(!hasPred && hasSucc)
- success = scheduleNode(*I, LateStart, (LateStart - II +1));
+ success = scheduleNode(*I, LateStart, (LateStart - II +1));
else if(hasPred && hasSucc) {
- if(EarlyStart > LateStart) {
- success = false;
- //LateStart = EarlyStart;
- DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
- }
- else
- success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
+ if(EarlyStart > LateStart) {
+ success = false;
+ //LateStart = EarlyStart;
+ DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
+ }
+ else
+ success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
}
else
- success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
+ success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
if(!success) {
- ++II;
- schedule.clear();
- break;
+ ++II;
+ schedule.clear();
+ break;
}
}
@@ -1928,8 +1928,8 @@
success = schedule.constructKernel(II, branches, indVarInstrs[BB]);
DEBUG(std::cerr << "Done Constructing Schedule Kernel\n");
if(!success) {
- ++II;
- schedule.clear();
+ ++II;
+ schedule.clear();
}
DEBUG(std::cerr << "Final II: " << II << "\n");
}
@@ -1947,7 +1947,7 @@
bool ModuloSchedulingPass::scheduleNode(MSchedGraphNode *node,
- int start, int end) {
+ int start, int end) {
bool success = false;
DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n");
@@ -1982,13 +1982,13 @@
++cycle;
DEBUG(std::cerr << "Increase cycle: " << cycle << "\n");
if(cycle > end)
- return false;
+ return false;
}
else {
--cycle;
DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n");
if(cycle < end)
- return false;
+ return false;
}
}
@@ -2030,79 +2030,79 @@
DEBUG(std::cerr << "i=" << i << "\n");
for(int j = i; j >= 0; --j) {
for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) {
- if(inKernel[j].count(&*MI)) {
- MachineInstr *instClone = MI->clone();
- machineBB->push_back(instClone);
-
- //If its a branch, insert a nop
- if(mii->isBranch(instClone->getOpcode()))
- BuildMI(machineBB, V9::NOP, 0);
-
-
- DEBUG(std::cerr << "Cloning: " << *MI << "\n");
-
- //After cloning, we may need to save the value that this instruction defines
- for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
- Instruction *tmp;
-
- //get machine operand
- MachineOperand &mOp = instClone->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
-
- //Check if this is a value we should save
- if(valuesToSave.count(mOp.getVRegValue())) {
- //Save copy in tmpInstruction
- tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Add TmpInstruction to safe LLVM Instruction MCFI
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n");
-
- newValues[mOp.getVRegValue()][i]= tmp;
- newValLocation[tmp] = machineBB;
-
- DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
-
- //Create machine instruction and put int machineBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
- }
- }
-
- //We may also need to update the value that we use if its from an earlier prologue
- if(j != 0) {
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i-1)) {
- Value *oldV = mOp.getVRegValue();
- DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
- //Update the operand with the right value
- mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
-
- //Remove this value since we have consumed it
- //NOTE: Should this only be done if j != maxStage?
- consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
- DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
- newValues[oldV].erase(i-1);
- }
- }
- else
- if(consumedValues.count(mOp.getVRegValue()))
- assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
- }
- }
- }
- }
+ if(inKernel[j].count(&*MI)) {
+ MachineInstr *instClone = MI->clone();
+ machineBB->push_back(instClone);
+
+ //If its a branch, insert a nop
+ if(mii->isBranch(instClone->getOpcode()))
+ BuildMI(machineBB, V9::NOP, 0);
+
+
+ DEBUG(std::cerr << "Cloning: " << *MI << "\n");
+
+ //After cloning, we may need to save the value that this instruction defines
+ for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
+ Instruction *tmp;
+
+ //get machine operand
+ MachineOperand &mOp = instClone->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+
+ //Check if this is a value we should save
+ if(valuesToSave.count(mOp.getVRegValue())) {
+ //Save copy in tmpInstruction
+ tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Add TmpInstruction to safe LLVM Instruction MCFI
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n");
+
+ newValues[mOp.getVRegValue()][i]= tmp;
+ newValLocation[tmp] = machineBB;
+
+ DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
+
+ //Create machine instruction and put int machineBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
+ }
+ }
+
+ //We may also need to update the value that we use if its from an earlier prologue
+ if(j != 0) {
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i-1)) {
+ Value *oldV = mOp.getVRegValue();
+ DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
+ //Update the operand with the right value
+ mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
+
+ //Remove this value since we have consumed it
+ //NOTE: Should this only be done if j != maxStage?
+ consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
+ DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
+ newValues[oldV].erase(i-1);
+ }
+ }
+ else
+ if(consumedValues.count(mOp.getVRegValue()))
+ assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
+ }
+ }
+ }
+ }
}
}
@@ -2158,53 +2158,53 @@
for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) {
for(int j=schedule.getMaxStage(); j > i; --j) {
- if(inKernel[j].count(&*MI)) {
- DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
- MachineInstr *clone = MI->clone();
-
- //Update operands that need to use the result from the phi
- for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
- //get machine operand
- const MachineOperand &mOp = clone->getOperand(opNum);
-
- if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
-
- DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
-
- //If this is the last instructions for the max iterations ago, don't update operands
- if(inEpilogue.count(mOp.getVRegValue()))
- if(inEpilogue[mOp.getVRegValue()] == i)
- continue;
-
- //Quickly write appropriate phis for this operand
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i)) {
- Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //assert of no kernelPHI for this value
- assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
-
- MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- valPHIs[mOp.getVRegValue()] = tmp;
- }
- }
-
- if(valPHIs.count(mOp.getVRegValue())) {
- //Update the operand in the cloned instruction
- clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
- }
- }
- else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
- inEpilogue[mOp.getVRegValue()] = i;
- }
- }
- machineBB->push_back(clone);
- }
+ if(inKernel[j].count(&*MI)) {
+ DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
+ MachineInstr *clone = MI->clone();
+
+ //Update operands that need to use the result from the phi
+ for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
+ //get machine operand
+ const MachineOperand &mOp = clone->getOperand(opNum);
+
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
+
+ DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
+
+ //If this is the last instructions for the max iterations ago, don't update operands
+ if(inEpilogue.count(mOp.getVRegValue()))
+ if(inEpilogue[mOp.getVRegValue()] == i)
+ continue;
+
+ //Quickly write appropriate phis for this operand
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i)) {
+ Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //assert of no kernelPHI for this value
+ assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
+
+ MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ valPHIs[mOp.getVRegValue()] = tmp;
+ }
+ }
+
+ if(valPHIs.count(mOp.getVRegValue())) {
+ //Update the operand in the cloned instruction
+ clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
+ }
+ }
+ else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
+ inEpilogue[mOp.getVRegValue()] = i;
+ }
+ }
+ machineBB->push_back(clone);
+ }
}
}
@@ -2259,64 +2259,64 @@
if(I->second != 0) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //Check to see where this operand is defined if this instruction is from max stage
- if(I->second == schedule.getMaxStage()) {
- DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
- }
-
- //If its in the value saved, we need to create a temp instruction and use that instead
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- //Check if we already have a final PHI value for this
- if(!finalPHIValue.count(mOp.getVRegValue())) {
- //Only create phi if the operand def is from a stage before this one
- if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //Update the operand in the cloned instruction
- instClone->getOperand(i).setValueReg(tmp);
-
- //save this as our final phi
- finalPHIValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB;
- }
- }
- else {
- //Use the previous final phi value
- instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
- }
- }
+ //Check to see where this operand is defined if this instruction is from max stage
+ if(I->second == schedule.getMaxStage()) {
+ DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
+ }
+
+ //If its in the value saved, we need to create a temp instruction and use that instead
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ //Check if we already have a final PHI value for this
+ if(!finalPHIValue.count(mOp.getVRegValue())) {
+ //Only create phi if the operand def is from a stage before this one
+ if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //Update the operand in the cloned instruction
+ instClone->getOperand(i).setValueReg(tmp);
+
+ //save this as our final phi
+ finalPHIValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB;
+ }
+ }
+ else {
+ //Use the previous final phi value
+ instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
+ }
+ }
}
}
if(I->second != schedule.getMaxStage()) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
- tempVec.addTemp((Value*) tmp);
-
- //Create new machine instr and put in MBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- //Save for future cleanup
- kernelValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB;
- kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
- }
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
+ tempVec.addTemp((Value*) tmp);
+
+ //Create new machine instr and put in MBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ //Save for future cleanup
+ kernelValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB;
+ kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
+ }
}
}
}
@@ -2342,7 +2342,7 @@
DEBUG(std::cerr << "Writing phi for" << *(V->first));
DEBUG(std::cerr << "\nMap of Value* for this phi\n");
DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
- IE = V->second.end(); I != IE; ++I) {
+ IE = V->second.end(); I != IE; ++I) {
std::cerr << "Stage: " << I->first;
std::cerr << " Value: " << *(I->second) << "\n";
});
@@ -2363,42 +2363,42 @@
unsigned count = 1;
//Loop over the the map backwards to generate phis
for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
- I != IE; ++I) {
+ I != IE; ++I) {
if(count < (V->second).size()) {
- if(lastPhi == 0) {
- lastPhi = new TmpInstruction(I->second);
+ if(lastPhi == 0) {
+ lastPhi = new TmpInstruction(I->second);
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) lastPhi);
-
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- newValLocation[lastPhi] = machineBB;
- }
- else {
- Instruction *tmp = new TmpInstruction(I->second);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
-
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- lastPhi = tmp;
- kernelPHIs[V->first][I->first] = lastPhi;
- newValLocation[lastPhi] = machineBB;
- }
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) lastPhi);
+
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ newValLocation[lastPhi] = machineBB;
+ }
+ else {
+ Instruction *tmp = new TmpInstruction(I->second);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ lastPhi = tmp;
+ kernelPHIs[V->first][I->first] = lastPhi;
+ newValLocation[lastPhi] = machineBB;
+ }
}
//Final phi value
else {
- //The resulting value must be the Value* we created earlier
- assert(lastPhi != 0 && "Last phi is NULL!\n");
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
+ //The resulting value must be the Value* we created earlier
+ assert(lastPhi != 0 && "Last phi is NULL!\n");
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
}
++count;
@@ -2436,55 +2436,55 @@
Instruction *tmp = 0;
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
- if(tmp->getType() == Type::FloatTy)
- BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
-
- worklist.push_back(std::make_pair(kernelBB, I));
- }
-
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+
+ worklist.push_back(std::make_pair(kernelBB, I));
+ }
+
}
}
@@ -2509,58 +2509,58 @@
DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
//Get op code and check if its a phi
if(I->getOpcode() == V9::PHI) {
- Instruction *tmp = 0;
+ Instruction *tmp = 0;
- for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- if(tmp->getType() == Type::FloatTy)
- BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
- worklist.push_back(std::make_pair(*MB,I));
- }
-
- }
+ for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+ worklist.push_back(std::make_pair(*MB,I));
+ }
+
+ }
}
@@ -2581,7 +2581,7 @@
DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
I->first->erase(I->second);
-
+
}
@@ -2615,64 +2615,64 @@
lastInstrs[inst] = I->second;
for(unsigned i=0; i < inst->getNumOperands(); ++i) {
- //get machine operand
- const MachineOperand &mOp = inst->getOperand(i);
-
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- if(isa<Constant>(srcI) || isa<Argument>(srcI))
- continue;
-
- //Before we declare this Value* one that we should save
- //make sure its def is not of the same stage as this instruction
- //because it will be consumed before its used
- Instruction *defInst = (Instruction*) srcI;
-
- //Should we save this value?
- bool save = true;
-
- //Continue if not in the def map, loop invariant code does not need to be saved
- if(!defMap.count(srcI))
- continue;
-
- MachineInstr *defInstr = defMap[srcI];
-
-
- if(lastInstrs.count(defInstr)) {
- if(lastInstrs[defInstr] == I->second) {
- save = false;
-
- }
- }
-
- if(save) {
- assert(!phiUses.count(srcI) && "Did not expect to see phi use twice");
- if(isa<PHINode>(srcI))
- phiUses[srcI] = I->second;
-
- valuesToSave[srcI] = std::make_pair(I->first, i);
-
- }
- }
- }
- else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- if (const Value* destI = mOp.getVRegValue()) {
- if(!isa<PHINode>(destI))
- continue;
- if(phiUses.count(destI)) {
- if(phiUses[destI] == I->second) {
- //remove from save list
- valuesToSave.erase(destI);
- }
- }
- }
- }
-
- if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
- }
+ //get machine operand
+ const MachineOperand &mOp = inst->getOperand(i);
+
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ if(isa<Constant>(srcI) || isa<Argument>(srcI))
+ continue;
+
+ //Before we declare this Value* one that we should save
+ //make sure its def is not of the same stage as this instruction
+ //because it will be consumed before its used
+ Instruction *defInst = (Instruction*) srcI;
+
+ //Should we save this value?
+ bool save = true;
+
+ //Continue if not in the def map, loop invariant code does not need to be saved
+ if(!defMap.count(srcI))
+ continue;
+
+ MachineInstr *defInstr = defMap[srcI];
+
+
+ if(lastInstrs.count(defInstr)) {
+ if(lastInstrs[defInstr] == I->second) {
+ save = false;
+
+ }
+ }
+
+ if(save) {
+ assert(!phiUses.count(srcI) && "Did not expect to see phi use twice");
+ if(isa<PHINode>(srcI))
+ phiUses[srcI] = I->second;
+
+ valuesToSave[srcI] = std::make_pair(I->first, i);
+
+ }
+ }
+ }
+ else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+ if (const Value* destI = mOp.getVRegValue()) {
+ if(!isa<PHINode>(destI))
+ continue;
+ if(phiUses.count(destI)) {
+ if(phiUses[destI] == I->second) {
+ //remove from save list
+ valuesToSave.erase(destI);
+ }
+ }
+ }
+ }
+
+ if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
+ }
}
}
}
@@ -2764,27 +2764,27 @@
//Find terminator since getFirstTerminator does not work!
for(MachineBasicBlock::reverse_iterator mInst = prologues[I]->rbegin(), mInstEnd = prologues[I]->rend(); mInst != mInstEnd; ++mInst) {
- MachineOpCode OC = mInst->getOpcode();
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we are branching to the kernel, if not branch to epilogue
- if(mOp.getVRegValue() == BB->getBasicBlock()) {
- if(I == prologues.size()-1)
- mOp.setValueReg(llvmKernelBB);
- else
- mOp.setValueReg(llvm_prologues[I+1]);
- }
- else {
- mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]);
- }
- }
- }
+ MachineOpCode OC = mInst->getOpcode();
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we are branching to the kernel, if not branch to epilogue
+ if(mOp.getVRegValue() == BB->getBasicBlock()) {
+ if(I == prologues.size()-1)
+ mOp.setValueReg(llvmKernelBB);
+ else
+ mOp.setValueReg(llvm_prologues[I+1]);
+ }
+ else {
+ mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]);
+ }
+ }
+ }
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
- }
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ }
}
@@ -2793,16 +2793,16 @@
const BranchInst *branchVal = dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
if(I == prologues.size()-1) {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- llvm_epilogues[(llvm_epilogues.size()-1-I)],
- branchVal->getCondition(),
- llvm_prologues[I]);
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
+ llvm_epilogues[(llvm_epilogues.size()-1-I)],
+ branchVal->getCondition(),
+ llvm_prologues[I]);
}
else
- TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1],
- llvm_epilogues[(llvm_epilogues.size()-1-I)],
- branchVal->getCondition(),
- llvm_prologues[I]);
+ TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1],
+ llvm_epilogues[(llvm_epilogues.size()-1-I)],
+ branchVal->getCondition(),
+ llvm_prologues[I]);
}
}
@@ -2814,21 +2814,21 @@
MachineOpCode OC = mInst->getOpcode();
if(TMI->isBranch(OC)) {
for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
-
- if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == BB->getBasicBlock())
- mOp.setValueReg(llvmKernelBB);
- else
- if(llvm_epilogues.size() > 0) {
- assert(origBranchExit == 0 && "There should only be one branch out of the loop");
-
- origBranchExit = mOp.getVRegValue();
- mOp.setValueReg(llvm_epilogues[0]);
- }
- else
- origBranchExit = mOp.getVRegValue();
- }
+ MachineOperand &mOp = mInst->getOperand(opNum);
+
+ if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == BB->getBasicBlock())
+ mOp.setValueReg(llvmKernelBB);
+ else
+ if(llvm_epilogues.size() > 0) {
+ assert(origBranchExit == 0 && "There should only be one branch out of the loop");
+
+ origBranchExit = mOp.getVRegValue();
+ mOp.setValueReg(llvm_epilogues[0]);
+ }
+ else
+ origBranchExit = mOp.getVRegValue();
+ }
}
}
}
@@ -2840,17 +2840,17 @@
if(epilogues.size() > 0) {
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- llvm_epilogues[0],
- branchVal->getCondition(),
- llvmKernelBB);
+ llvm_epilogues[0],
+ branchVal->getCondition(),
+ llvmKernelBB);
}
else {
BasicBlock *origBBExit = dyn_cast<BasicBlock>(origBranchExit);
assert(origBBExit !=0 && "Original exit basic block must be set");
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- origBBExit,
- branchVal->getCondition(),
- llvmKernelBB);
+ origBBExit,
+ branchVal->getCondition(),
+ llvmKernelBB);
}
if(schedule.getMaxStage() != 0) {
@@ -2862,7 +2862,7 @@
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(llvm_epilogues[I+1]);
//Add unconditional branch to end of epilogue
TerminatorInst *newBranch = new BranchInst(llvm_epilogues[I+1],
- llvm_epilogues[I]);
+ llvm_epilogues[I]);
}
else {
@@ -2874,8 +2874,8 @@
//Find where we are supposed to branch to
BasicBlock *nextBlock = 0;
for(unsigned j=0; j <branchVal->getNumSuccessors(); ++j) {
- if(branchVal->getSuccessor(j) != BB->getBasicBlock())
- nextBlock = branchVal->getSuccessor(j);
+ if(branchVal->getSuccessor(j) != BB->getBasicBlock())
+ nextBlock = branchVal->getSuccessor(j);
}
assert((nextBlock != 0) && "Next block should not be null!");
@@ -2907,51 +2907,51 @@
//Update the terminator
TerminatorInst *term = ((BasicBlock*)*P)->getTerminator();
for(unsigned i=0; i < term->getNumSuccessors(); ++i) {
- if(term->getSuccessor(i) == llvmBB) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- if(llvm_prologues.size() > 0) {
- term->setSuccessor(i, llvm_prologues[0]);
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvm_prologues[0]);
- }
- }
- }
- }
- }
- else {
- term->setSuccessor(i, llvmKernelBB);
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvmKernelBB);
- }
- }
- }
- }
- }
- }
+ if(term->getSuccessor(i) == llvmBB) {
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ if(llvm_prologues.size() > 0) {
+ term->setSuccessor(i, llvm_prologues[0]);
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvm_prologues[0]);
+ }
+ }
+ }
+ }
+ }
+ else {
+ term->setSuccessor(i, llvmKernelBB);
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvmKernelBB);
+ }
+ }
+ }
+ }
+ }
+ }
}
break;
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.31 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.32
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h:1.31 Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.h Wed Jul 27 00:53:44 2005
@@ -34,9 +34,9 @@
int depth;
int height;
MSNodeAttributes(int asap=-1, int alap=-1, int mob=-1,
- int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
- MOB(mob), depth(d),
- height(h) {}
+ int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
+ MOB(mob), depth(d),
+ height(h) {}
};
@@ -80,7 +80,7 @@
bool CreateDefMap(MachineBasicBlock *BI);
bool MachineBBisValid(const MachineBasicBlock *BI);
bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack, BasicBlock *BB);
+ std::vector<Instruction*> &stack, BasicBlock *BB);
int calculateResMII(const MachineBasicBlock *BI);
int calculateRecMII(MSchedGraph *graph, int MII);
void calculateNodeAttributes(MSchedGraph *graph, int MII);
@@ -96,36 +96,36 @@
int findMaxASAP();
void orderNodes();
void findAllReccurrences(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &visitedNodes, int II);
+ std::vector<MSchedGraphNode*> &visitedNodes, int II);
void addReccurrence(std::vector<MSchedGraphNode*> &recurrence, int II, MSchedGraphNode*, MSchedGraphNode*);
void addSCC(std::vector<MSchedGraphNode*> &SCC, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
void findAllCircuits(MSchedGraph *MSG, int II);
bool circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
- std::set<MSchedGraphNode*> &blocked,
- std::vector<MSchedGraphNode*> &SCC, MSchedGraphNode *s,
- std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B, int II,
- std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
+ std::set<MSchedGraphNode*> &blocked,
+ std::vector<MSchedGraphNode*> &SCC, MSchedGraphNode *s,
+ std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B, int II,
+ std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
void unblock(MSchedGraphNode *u, std::set<MSchedGraphNode*> &blocked,
- std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B);
+ std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B);
void addRecc(std::vector<MSchedGraphNode*> &stack, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
- void searchPath(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &nodesToAdd,
- std::set<MSchedGraphNode*> &new_reccurence);
+ void searchPath(MSchedGraphNode *node,
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &nodesToAdd,
+ std::set<MSchedGraphNode*> &new_reccurence);
void pathToRecc(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &poSet, std::set<MSchedGraphNode*> &lastNodes);
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &poSet, std::set<MSchedGraphNode*> &lastNodes);
void computePartialOrder();
bool computeSchedule(const MachineBasicBlock *BB, MSchedGraph *MSG);
- bool scheduleNode(MSchedGraphNode *node,
- int start, int end);
+ bool scheduleNode(MSchedGraphNode *node,
+ int start, int end);
void predIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult);
void succIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult);
@@ -159,7 +159,7 @@
/// before we run.
AU.addRequired<LoopInfo>();
AU.addRequired<ScalarEvolution>();
-
+
AU.addRequired<DependenceAnalyzer>();
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.3 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.4
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp:1.3 Fri Jul 1 01:40:58 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.cpp Wed Jul 27 00:53:44 2005
@@ -74,11 +74,11 @@
Statistic<> NumSB("moduloschedSB-numSuperBlocks", "Total Number of SuperBlocks");
Statistic<> BBWithCalls("modulosched-BBCalls", "Basic Blocks rejected due to calls");
Statistic<> BBWithCondMov("modulosched-loopCondMov",
- "Basic Blocks rejected due to conditional moves");
+ "Basic Blocks rejected due to conditional moves");
Statistic<> SBResourceConstraint("modulosched-resourceConstraint",
- "Loops constrained by resources");
+ "Loops constrained by resources");
Statistic<> SBRecurrenceConstraint("modulosched-recurrenceConstraint",
- "Loops constrained by recurrences");
+ "Loops constrained by recurrences");
Statistic<> SBFinalIISum("modulosched-finalIISum", "Sum of all final II");
Statistic<> SBIISum("modulosched-IISum", "Sum of all theoretical II");
Statistic<> SBMSLoops("modulosched-schedLoops", "Number of loops successfully modulo-scheduled");
@@ -97,42 +97,42 @@
static std::string getNodeLabel(MSchedGraphSBNode *Node, MSchedGraphSB *Graph) {
if(!Node->isPredicate()) {
- if (Node->getInst()) {
- std::stringstream ss;
- ss << *(Node->getInst());
- return ss.str(); //((MachineInstr*)Node->getInst());
- }
- else
- return "No Inst";
+ if (Node->getInst()) {
+ std::stringstream ss;
+ ss << *(Node->getInst());
+ return ss.str(); //((MachineInstr*)Node->getInst());
+ }
+ else
+ return "No Inst";
}
else
- return "Pred Node";
+ return "Pred Node";
}
static std::string getEdgeSourceLabel(MSchedGraphSBNode *Node,
- MSchedGraphSBNode::succ_iterator I) {
+ MSchedGraphSBNode::succ_iterator I) {
//Label each edge with the type of dependence
std::string edgelabel = "";
switch (I.getEdge().getDepOrderType()) {
-
+
case MSchedGraphSBEdge::TrueDep:
- edgelabel = "True";
- break;
+ edgelabel = "True";
+ break;
case MSchedGraphSBEdge::AntiDep:
- edgelabel = "Anti";
- break;
-
+ edgelabel = "Anti";
+ break;
+
case MSchedGraphSBEdge::OutputDep:
- edgelabel = "Output";
- break;
-
+ edgelabel = "Output";
+ break;
+
case MSchedGraphSBEdge::NonDataDep:
- edgelabel = "Pred";
- break;
+ edgelabel = "Pred";
+ break;
default:
- edgelabel = "Unknown";
- break;
+ edgelabel = "Unknown";
+ break;
}
//FIXME
@@ -165,22 +165,22 @@
//Loop over worklist and ModuloSchedule each SuperBlock
for(std::vector<std::vector<const MachineBasicBlock*> >::iterator SB = Worklist.begin(),
- SBE = Worklist.end(); SB != SBE; ++SB) {
+ SBE = Worklist.end(); SB != SBE; ++SB) {
//Print out Superblock
DEBUG(std::cerr << "ModuloScheduling SB: \n";
- for(std::vector<const MachineBasicBlock*>::const_iterator BI = SB->begin(),
- BE = SB->end(); BI != BE; ++BI) {
- (*BI)->print(std::cerr);});
+ for(std::vector<const MachineBasicBlock*>::const_iterator BI = SB->begin(),
+ BE = SB->end(); BI != BE; ++BI) {
+ (*BI)->print(std::cerr);});
if(!CreateDefMap(*SB)) {
- defaultInst = 0;
- defMap.clear();
- continue;
+ defaultInst = 0;
+ defMap.clear();
+ continue;
}
MSchedGraphSB *MSG = new MSchedGraphSB(*SB, target, indVarInstrs[*SB], DA,
- machineTollvm[*SB]);
+ machineTollvm[*SB]);
//Write Graph out to file
DEBUG(WriteGraphToFileSB(std::cerr, F.getName(), MSG));
@@ -195,9 +195,9 @@
//Our starting initiation interval is the maximum of RecMII and ResMII
if(RecMII < ResMII)
- ++SBRecurrenceConstraint;
+ ++SBRecurrenceConstraint;
else
- ++SBResourceConstraint;
+ ++SBResourceConstraint;
II = std::max(RecMII, ResMII);
int mII = II;
@@ -211,11 +211,11 @@
//Dump node properties if in debug mode
DEBUG(for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
- << " Height: " << I->second.height << "\n";
- });
+ E = nodeToAttributesMap.end(); I !=E; ++I) {
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ << " Height: " << I->second.height << "\n";
+ });
//Put nodes in order to schedule them
@@ -223,19 +223,19 @@
//Dump out partial order
DEBUG(for(std::vector<std::set<MSchedGraphSBNode*> >::iterator I = partialOrder.begin(),
- E = partialOrder.end(); I !=E; ++I) {
- std::cerr << "Start set in PO\n";
- for(std::set<MSchedGraphSBNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
- std::cerr << "PO:" << **J << "\n";
- });
+ E = partialOrder.end(); I !=E; ++I) {
+ std::cerr << "Start set in PO\n";
+ for(std::set<MSchedGraphSBNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+ std::cerr << "PO:" << **J << "\n";
+ });
//Place nodes in final order
orderNodes();
//Dump out order of nodes
DEBUG(for(std::vector<MSchedGraphSBNode*>::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) {
- std::cerr << "FO:" << **I << "\n";
- });
+ std::cerr << "FO:" << **I << "\n";
+ });
//Finally schedule nodes
@@ -247,18 +247,18 @@
//Final scheduling step is to reconstruct the loop only if we actual have
//stage > 0
if(haveSched) {
- //schedule.printSchedule(std::cerr);
- reconstructLoop(*SB);
- ++SBMSLoops;
- //Changed = true;
- SBIISum += mII;
- SBFinalIISum += II;
-
+ //schedule.printSchedule(std::cerr);
+ reconstructLoop(*SB);
+ ++SBMSLoops;
+ //Changed = true;
+ SBIISum += mII;
+ SBFinalIISum += II;
+
if(schedule.getMaxStage() == 0)
- ++SBSameStage;
+ ++SBSameStage;
}
else
- ++SBNoSched;
+ ++SBNoSched;
//Clear out our maps for the next basic block that is processed
nodeToAttributesMap.clear();
@@ -273,7 +273,7 @@
}
void ModuloSchedulingSBPass::FindSuperBlocks(Function &F, LoopInfo &LI,
- std::vector<std::vector<const MachineBasicBlock*> > &Worklist) {
+ std::vector<std::vector<const MachineBasicBlock*> > &Worklist) {
//Get MachineFunction
MachineFunction &MF = MachineFunction::get(&F);
@@ -294,95 +294,95 @@
//If loop is not single entry, try the next one
if(!L->getLoopPreheader())
- continue;
+ continue;
//Check size of this loop, we don't want SBB loops
if(L->getBlocks().size() == 1)
- continue;
+ continue;
//Check if this loop contains no sub loops
if(L->getSubLoops().size() == 0) {
-
- std::vector<const MachineBasicBlock*> superBlock;
-
- //Get Loop Headers
- BasicBlock *header = L->getHeader();
-
- //Follow the header and make sure each BB only has one entry and is valid
- BasicBlock *current = header;
- assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB\n");
- MachineBasicBlock *currentMBB = bbMap[header];
- bool done = false;
- bool success = true;
- unsigned offset = 0;
- std::map<const MachineInstr*, unsigned> indexMap;
-
- while(!done) {
- //Loop over successors of this BB, they should be in the
- //loop block and be valid
- BasicBlock *next = 0;
- for(succ_iterator I = succ_begin(current), E = succ_end(current);
- I != E; ++I) {
- if(L->contains(*I)) {
- if(!next)
- next = *I;
- else {
- done = true;
- success = false;
- break;
- }
- }
- }
-
- if(success) {
- superBlock.push_back(currentMBB);
- if(next == header)
- done = true;
- else if(!next->getSinglePredecessor()) {
- done = true;
- success = false;
- }
- else {
- //Check that the next BB only has one entry
- current = next;
- assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB");
- currentMBB = bbMap[current];
- }
- }
- }
-
-
-
-
-
- if(success) {
- ++NumSB;
-
- //Loop over all the blocks in the superblock
- for(std::vector<const MachineBasicBlock*>::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) {
- if(!MachineBBisValid(*currentMBB, indexMap, offset)) {
- success = false;
- break;
- }
- }
- }
-
- if(success) {
- if(getIndVar(superBlock, bbMap, indexMap)) {
- ++SBValid;
- Worklist.push_back(superBlock);
- SBSize += superBlock.size();
- }
- else
- ++SBInvalid;
- }
+
+ std::vector<const MachineBasicBlock*> superBlock;
+
+ //Get Loop Headers
+ BasicBlock *header = L->getHeader();
+
+ //Follow the header and make sure each BB only has one entry and is valid
+ BasicBlock *current = header;
+ assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB\n");
+ MachineBasicBlock *currentMBB = bbMap[header];
+ bool done = false;
+ bool success = true;
+ unsigned offset = 0;
+ std::map<const MachineInstr*, unsigned> indexMap;
+
+ while(!done) {
+ //Loop over successors of this BB, they should be in the
+ //loop block and be valid
+ BasicBlock *next = 0;
+ for(succ_iterator I = succ_begin(current), E = succ_end(current);
+ I != E; ++I) {
+ if(L->contains(*I)) {
+ if(!next)
+ next = *I;
+ else {
+ done = true;
+ success = false;
+ break;
+ }
+ }
+ }
+
+ if(success) {
+ superBlock.push_back(currentMBB);
+ if(next == header)
+ done = true;
+ else if(!next->getSinglePredecessor()) {
+ done = true;
+ success = false;
+ }
+ else {
+ //Check that the next BB only has one entry
+ current = next;
+ assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB");
+ currentMBB = bbMap[current];
+ }
+ }
+ }
+
+
+
+
+
+ if(success) {
+ ++NumSB;
+
+ //Loop over all the blocks in the superblock
+ for(std::vector<const MachineBasicBlock*>::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) {
+ if(!MachineBBisValid(*currentMBB, indexMap, offset)) {
+ success = false;
+ break;
+ }
+ }
+ }
+
+ if(success) {
+ if(getIndVar(superBlock, bbMap, indexMap)) {
+ ++SBValid;
+ Worklist.push_back(superBlock);
+ SBSize += superBlock.size();
+ }
+ else
+ ++SBInvalid;
+ }
}
}
}
bool ModuloSchedulingSBPass::getIndVar(std::vector<const MachineBasicBlock*> &superBlock, std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- std::map<const MachineInstr*, unsigned> &indexMap) {
+ std::map<const MachineInstr*, unsigned> &indexMap) {
//See if we can get induction var instructions
std::set<const BasicBlock*> llvmSuperBlock;
@@ -409,14 +409,14 @@
indVar.insert(b);
if(Instruction *I = dyn_cast<Instruction>(cond))
- if(bbMap.count(I->getParent())) {
- if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock))
- return false;
- }
- else
- return false;
+ if(bbMap.count(I->getParent())) {
+ if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock))
+ return false;
+ }
+ else
+ return false;
else
- return false;
+ return false;
}
else {
indVar.insert(b);
@@ -424,43 +424,43 @@
//Dump out instructions associate with indvar for debug reasons
DEBUG(for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end();
- N != NE; ++N) {
- std::cerr << **N << "\n";
- });
+ N != NE; ++N) {
+ std::cerr << **N << "\n";
+ });
//Create map of machine instr to llvm instr
std::map<MachineInstr*, Instruction*> mllvm;
for(std::vector<const MachineBasicBlock*>::iterator MBB = superBlock.begin(), MBE = superBlock.end(); MBB != MBE; ++MBB) {
BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock();
for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- mllvm[tempMvec[j]] = I;
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ mllvm[tempMvec[j]] = I;
+ }
}
}
//Convert list of LLVM Instructions to list of Machine instructions
std::map<const MachineInstr*, unsigned> mIndVar;
for(std::set<Instruction*>::iterator N = indVar.begin(),
- NE = indVar.end(); N != NE; ++N) {
-
- //If we have a load, we can't handle this loop because
- //there is no way to preserve dependences between loads
- //and stores
- if(isa<LoadInst>(*N))
- return false;
-
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineOpCode OC = (tempMvec[j])->getOpcode();
- if(TMI->isNop(OC))
- continue;
- if(!indexMap.count(tempMvec[j]))
- continue;
- mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
- DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
- }
+ NE = indVar.end(); N != NE; ++N) {
+
+ //If we have a load, we can't handle this loop because
+ //there is no way to preserve dependences between loads
+ //and stores
+ if(isa<LoadInst>(*N))
+ return false;
+
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineOpCode OC = (tempMvec[j])->getOpcode();
+ if(TMI->isNop(OC))
+ continue;
+ if(!indexMap.count(tempMvec[j]))
+ continue;
+ mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
+ DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
+ }
}
//Put into a map for future access
@@ -472,38 +472,38 @@
}
bool ModuloSchedulingSBPass::assocIndVar(Instruction *I,
- std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack,
- std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- const BasicBlock *last, std::set<const BasicBlock*> &llvmSuperBlock) {
+ std::set<Instruction*> &indVar,
+ std::vector<Instruction*> &stack,
+ std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+ const BasicBlock *last, std::set<const BasicBlock*> &llvmSuperBlock) {
stack.push_back(I);
//If this is a phi node, check if its the canonical indvar
if(PHINode *PN = dyn_cast<PHINode>(I)) {
if(llvmSuperBlock.count(PN->getParent())) {
- if (Instruction *Inc =
- dyn_cast<Instruction>(PN->getIncomingValueForBlock(last)))
- if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
- if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
- if (CI->equalsInt(1)) {
- //We have found the indvar, so add the stack, and inc instruction to the set
- indVar.insert(stack.begin(), stack.end());
- indVar.insert(Inc);
- stack.pop_back();
- return true;
- }
- return false;
+ if (Instruction *Inc =
+ dyn_cast<Instruction>(PN->getIncomingValueForBlock(last)))
+ if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
+ if (CI->equalsInt(1)) {
+ //We have found the indvar, so add the stack, and inc instruction to the set
+ indVar.insert(stack.begin(), stack.end());
+ indVar.insert(Inc);
+ stack.pop_back();
+ return true;
+ }
+ return false;
}
}
else {
//Loop over each of the instructions operands, check if they are an instruction and in this BB
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- if(Instruction *N = dyn_cast<Instruction>(I->getOperand(i))) {
- if(bbMap.count(N->getParent()))
- if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock))
- return false;
- }
+ if(Instruction *N = dyn_cast<Instruction>(I->getOperand(i))) {
+ if(bbMap.count(N->getParent()))
+ if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock))
+ return false;
+ }
}
}
@@ -517,8 +517,8 @@
/// calls) in the block. Currently ModuloScheduling only works on
/// single basic block loops.
bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI,
- std::map<const MachineInstr*, unsigned> &indexMap,
- unsigned &offset) {
+ std::map<const MachineInstr*, unsigned> &indexMap,
+ unsigned &offset) {
//Check size of our basic block.. make sure we have more then just the terminator in it
if(BI->getBasicBlock()->size() == 1)
@@ -534,26 +534,26 @@
//Look for calls
if(TMI->isCall(OC)) {
- ++BBWithCalls;
- return false;
+ ++BBWithCalls;
+ return false;
}
//Look for conditional move
if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi
- || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
- || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr
- || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr
- || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi
- || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi
- || OC == V9::MOVFNEr || OC == V9::MOVFNEi) {
- ++BBWithCondMov;
- return false;
+ || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
+ || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr
+ || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr
+ || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi
+ || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi
+ || OC == V9::MOVFNEr || OC == V9::MOVFNEi) {
+ ++BBWithCondMov;
+ return false;
}
indexMap[I] = count + offset;
if(TMI->isNop(OC))
- continue;
+ continue;
++count;
}
@@ -568,30 +568,30 @@
defaultInst = 0;
for(std::vector<const MachineBasicBlock*>::iterator BI = SB.begin(),
- BE = SB.end(); BI != BE; ++BI) {
+ BE = SB.end(); BI != BE; ++BI) {
for(MachineBasicBlock::const_iterator I = (*BI)->begin(), E = (*BI)->end(); I != E; ++I) {
for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) {
- const MachineOperand &mOp = I->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- Value *V = mOp.getVRegValue();
- //assert if this is the second def we have seen
- if(defMap.count(V) && isa<PHINode>(V))
- DEBUG(std::cerr << "FIXME: Dup def for phi!\n");
- else {
- //assert(!defMap.count(V) && "Def already in the map");
- if(defMap.count(V))
- return false;
- defMap[V] = (MachineInstr*) &*I;
- }
- }
-
- //See if we can use this Value* as our defaultInst
- if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
- Value *V = mOp.getVRegValue();
- if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
- defaultInst = (Instruction*) V;
- }
+ const MachineOperand &mOp = I->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+ Value *V = mOp.getVRegValue();
+ //assert if this is the second def we have seen
+ if(defMap.count(V) && isa<PHINode>(V))
+ DEBUG(std::cerr << "FIXME: Dup def for phi!\n");
+ else {
+ //assert(!defMap.count(V) && "Def already in the map");
+ if(defMap.count(V))
+ return false;
+ defMap[V] = (MachineInstr*) &*I;
+ }
+ }
+
+ //See if we can use this Value* as our defaultInst
+ if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
+ Value *V = mOp.getVRegValue();
+ if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
+ defaultInst = (Instruction*) V;
+ }
}
}
}
@@ -629,14 +629,14 @@
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i)
- for(unsigned j=0; j < resources[i].size(); ++j) {
- if(!resourceUsageCount.count(resources[i][j])) {
- resourceUsageCount[resources[i][j]] = 1;
- }
- else {
- resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
- }
- }
+ for(unsigned j=0; j < resources[i].size(); ++j) {
+ if(!resourceUsageCount.count(resources[i][j])) {
+ resourceUsageCount[resources[i][j]] = 1;
+ }
+ else {
+ resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
+ }
+ }
}
}
@@ -692,7 +692,7 @@
int CircCountSB;
void ModuloSchedulingSBPass::unblock(MSchedGraphSBNode *u, std::set<MSchedGraphSBNode*> &blocked,
- std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B) {
+ std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B) {
//Unblock u
DEBUG(std::cerr << "Unblocking: " << *u << "\n");
@@ -726,13 +726,13 @@
for(unsigned i = 0; i < (*N)->succ_size(); ++i) {
MSchedGraphSBEdge *edge = (*N)->getSuccessor(i);
if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) {
- totalDistance += edge->getIteDiff();
- if(edge->getIteDiff() > 0)
- if(!start && !end) {
- start = *N;
- end = edge->getDest();
- }
-
+ totalDistance += edge->getIteDiff();
+ if(edge->getIteDiff() > 0)
+ if(!start && !end) {
+ start = *N;
+ end = edge->getDest();
+ }
+
}
}
@@ -748,7 +748,7 @@
assert( (start && end) && "Must have start and end node to ignore edge for SCC");
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
@@ -762,9 +762,9 @@
}
bool ModuloSchedulingSBPass::circuit(MSchedGraphSBNode *v, std::vector<MSchedGraphSBNode*> &stack,
- std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
- MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B,
- int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
+ std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
+ MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B,
+ int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
bool f = false;
DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n");
@@ -791,7 +791,7 @@
}
else if(!blocked.count(*I)) {
if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes))
- f = true;
+ f = true;
}
else
DEBUG(std::cerr << "Blocked: " << **I << "\n");
@@ -818,7 +818,7 @@
std::vector<MSchedGraphSBNode*> recc;
//Dump recurrence for now
DEBUG(std::cerr << "Starting Recc\n");
-
+
int totalDelay = 0;
int totalDistance = 0;
MSchedGraphSBNode *lastN = 0;
@@ -834,8 +834,8 @@
totalDistance += iteDiff;
if(iteDiff > 0) {
- start = lastN;
- end = *N;
+ start = lastN;
+ end = *N;
}
}
//Get the original node
@@ -851,7 +851,7 @@
DEBUG(std::cerr << "End Recc\n");
CircCountSB++;
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
@@ -867,7 +867,7 @@
int value = totalDelay-(RecMII * totalDistance);
int lastII = II;
while(value < 0) {
-
+
lastII = RecMII;
RecMII--;
value = totalDelay-(RecMII * totalDistance);
@@ -921,64 +921,64 @@
//Find scc with the least vertex
for (MSchedGraphSB::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI)
if (Visited.insert(GI->second).second) {
- for (scc_iterator<MSchedGraphSBNode*> SCCI = scc_begin(GI->second),
- E = scc_end(GI->second); SCCI != E; ++SCCI) {
- std::vector<MSchedGraphSBNode*> &nextSCC = *SCCI;
-
- if (Visited.insert(nextSCC[0]).second) {
- Visited.insert(nextSCC.begin()+1, nextSCC.end());
-
- if(nextSCC.size() > 1) {
- DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n");
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- //Loop over successor and see if in scc, then count edge
- MSchedGraphSBNode *node = nextSCC[i];
- for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
- if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
- numEdges++;
- }
- }
- DEBUG(std::cerr << "Num Edges: " << numEdges << "\n");
- }
-
- //Ignore self loops
- if(nextSCC.size() > 1) {
-
- //Get least vertex in Vk
- if(!s) {
- s = nextSCC[0];
- Vk = nextSCC;
- }
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- if(nextSCC[i] < s) {
- s = nextSCC[i];
- Vk = nextSCC;
- }
- }
- }
- }
- }
+ for (scc_iterator<MSchedGraphSBNode*> SCCI = scc_begin(GI->second),
+ E = scc_end(GI->second); SCCI != E; ++SCCI) {
+ std::vector<MSchedGraphSBNode*> &nextSCC = *SCCI;
+
+ if (Visited.insert(nextSCC[0]).second) {
+ Visited.insert(nextSCC.begin()+1, nextSCC.end());
+
+ if(nextSCC.size() > 1) {
+ DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n");
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ //Loop over successor and see if in scc, then count edge
+ MSchedGraphSBNode *node = nextSCC[i];
+ for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
+ if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
+ numEdges++;
+ }
+ }
+ DEBUG(std::cerr << "Num Edges: " << numEdges << "\n");
+ }
+
+ //Ignore self loops
+ if(nextSCC.size() > 1) {
+
+ //Get least vertex in Vk
+ if(!s) {
+ s = nextSCC[0];
+ Vk = nextSCC;
+ }
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ if(nextSCC[i] < s) {
+ s = nextSCC[i];
+ Vk = nextSCC;
+ }
+ }
+ }
+ }
+ }
}
//Process SCC
DEBUG(for(std::vector<MSchedGraphSBNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) { std::cerr << *((*N)->getInst()); });
+ N != NE; ++N) { std::cerr << *((*N)->getInst()); });
//Iterate over all nodes in this scc
for(std::vector<MSchedGraphSBNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) {
+ N != NE; ++N) {
blocked.erase(*N);
B[*N].clear();
}
if(Vk.size() > 1) {
if(numEdges < 98)
- circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+ circuit(s, stack, blocked, Vk, s, B, II, newNodes);
else
- addSCC(Vk, newNodes);
+ addSCC(Vk, newNodes);
//Delete nodes from the graph
@@ -986,12 +986,12 @@
std::vector<MSchedGraphSBNode*> nodesToRemove;
nodesToRemove.push_back(s);
for(MSchedGraphSB::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) {
- if(N->second < s )
- nodesToRemove.push_back(N->second);
+ if(N->second < s )
+ nodesToRemove.push_back(N->second);
}
for(std::vector<MSchedGraphSBNode*>::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) {
- DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
- MSG->deleteNode(*N);
+ DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
+ MSG->deleteNode(*N);
}
}
else
@@ -1015,7 +1015,7 @@
//Assert if its already in the map
assert(nodeToAttributesMap.count(I->second) == 0 &&
- "Node attributes are already in the map");
+ "Node attributes are already in the map");
//Put into the map with default attribute values
nodeToAttributesMap[I->second] = MSNodeSBAttributes();
@@ -1101,7 +1101,7 @@
int ModuloSchedulingSBPass::calculateALAP(MSchedGraphSBNode *node, int MII,
- int maxASAP, MSchedGraphSBNode *srcNode) {
+ int maxASAP, MSchedGraphSBNode *srcNode) {
DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n");
@@ -1122,28 +1122,28 @@
//Iterate over all of the predecessors and fine max
for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
//Only process if we are not ignoring the edge
if(!ignoreEdge(node, *P)) {
- processedOneEdge = true;
- int succALAP = -1;
- succALAP = calculateALAP(*P, MII, maxASAP, node);
-
- assert(succALAP != -1 && "Successors ALAP should have been caclulated");
-
- int iteDiff = P.getEdge().getIteDiff();
-
- int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
-
- DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
+ processedOneEdge = true;
+ int succALAP = -1;
+ succALAP = calculateALAP(*P, MII, maxASAP, node);
+
+ assert(succALAP != -1 && "Successors ALAP should have been caclulated");
+
+ int iteDiff = P.getEdge().getIteDiff();
+
+ int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
+
+ DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
- minSuccValue = std::min(minSuccValue, currentSuccValue);
+ minSuccValue = std::min(minSuccValue, currentSuccValue);
}
}
if(processedOneEdge)
- attributes.ALAP = minSuccValue;
+ attributes.ALAP = minSuccValue;
else
attributes.ALAP = maxASAP;
@@ -1163,7 +1163,7 @@
int maxASAP = 0;
for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I)
+ E = nodeToAttributesMap.end(); I != E; ++I)
maxASAP = std::max(maxASAP, I->second.ASAP);
return maxASAP;
}
@@ -1180,7 +1180,7 @@
//Iterate over all of the predecessors and find max
for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
if(!ignoreEdge(node, *P)) {
@@ -1199,7 +1199,7 @@
int ModuloSchedulingSBPass::calculateDepth(MSchedGraphSBNode *node,
- MSchedGraphSBNode *destNode) {
+ MSchedGraphSBNode *destNode) {
MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second;
@@ -1239,24 +1239,24 @@
//along with any nodes that connect this recurrence to recurrences
//already in the partial order
for(std::set<std::pair<int, std::vector<MSchedGraphSBNode*> > >::reverse_iterator
- I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
+ I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
std::set<MSchedGraphSBNode*> new_recurrence;
//Loop through recurrence and remove any nodes already in the partial order
for(std::vector<MSchedGraphSBNode*>::const_iterator N = I->second.begin(),
- NE = I->second.end(); N != NE; ++N) {
+ NE = I->second.end(); N != NE; ++N) {
bool found = false;
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
}
//Check if its a branch, and remove to handle special
if(!found) {
- new_recurrence.insert(*N);
+ new_recurrence.insert(*N);
}
}
@@ -1274,21 +1274,21 @@
//Add nodes that connect this recurrence to recurrences in the partial path
for(std::set<MSchedGraphSBNode*>::iterator N = new_recurrence.begin(),
NE = new_recurrence.end(); N != NE; ++N)
- searchPath(*N, path, nodesToAdd, new_recurrence);
+ searchPath(*N, path, nodesToAdd, new_recurrence);
//Add nodes to this recurrence if they are not already in the partial order
for(std::set<MSchedGraphSBNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
- N != NE; ++N) {
- bool found = false;
- for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
- }
- if(!found) {
- assert("FOUND CONNECTOR");
- new_recurrence.insert(*N);
- }
+ N != NE; ++N) {
+ bool found = false;
+ for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
+ }
+ if(!found) {
+ assert("FOUND CONNECTOR");
+ new_recurrence.insert(*N);
+ }
}
partialOrder.push_back(new_recurrence);
@@ -1300,15 +1300,15 @@
std::set<MSchedGraphSBNode*> lastNodes;
std::set<MSchedGraphSBNode*> noPredNodes;
for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I) {
+ E = nodeToAttributesMap.end(); I != E; ++I) {
bool found = false;
//Check if its already in our partial order, if not add it to the final vector
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(I->first))
- found = true;
+ found = true;
}
if(!found)
lastNodes.insert(I->first);
@@ -1320,7 +1320,7 @@
N != NE; ++N) {
DEBUG(std::cerr << "No Pred Path from: " << **N << "\n");
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
std::vector<MSchedGraphSBNode*> path;
pathToRecc(*N, path, *PO, lastNodes);
}
@@ -1333,7 +1333,7 @@
std::set<MSchedGraphSBNode*> ccSet;
connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes);
if(ccSet.size() > 0)
- partialOrder.push_back(ccSet);
+ partialOrder.push_back(ccSet);
}
}
@@ -1356,9 +1356,9 @@
}
void ModuloSchedulingSBPass::searchPath(MSchedGraphSBNode *node,
- std::vector<MSchedGraphSBNode*> &path,
- std::set<MSchedGraphSBNode*> &nodesToAdd,
- std::set<MSchedGraphSBNode*> &new_reccurrence) {
+ std::vector<MSchedGraphSBNode*> &path,
+ std::set<MSchedGraphSBNode*> &nodesToAdd,
+ std::set<MSchedGraphSBNode*> &new_reccurrence) {
//Push node onto the path
path.push_back(node);
@@ -1381,11 +1381,11 @@
//final vector
bool found = false;
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(*S)) {
- found = true;
- break;
+ found = true;
+ break;
}
}
@@ -1420,8 +1420,8 @@
/*for(std::vector<std::set<MSchedGraphSBNode*> >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) {
for(std::set<MSchedGraphSBNode*>::iterator N = CurrentSet->begin(), NE = CurrentSet->end(); N != NE; ++N)
if((*N)->isPredicate()) {
- FinalNodeOrder.push_back(*N);
- CurrentSet->erase(*N);
+ FinalNodeOrder.push_back(*N);
+ CurrentSet->erase(*N);
}
}*/
@@ -1452,28 +1452,28 @@
//sort top-down
if(IntersectCurrent.size() != 0) {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
- order = TOP_DOWN;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
+ order = TOP_DOWN;
}
else {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
- //Find node with max ASAP in current Set
- MSchedGraphSBNode *node;
- int maxASAP = 0;
- DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
- for(std::set<MSchedGraphSBNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
- //Get node attributes
- MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
- //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
-
- if(maxASAP <= nodeAttr.ASAP) {
- maxASAP = nodeAttr.ASAP;
- node = *J;
- }
- }
- assert(node != 0 && "In node ordering node should not be null");
- IntersectCurrent.insert(node);
- order = BOTTOM_UP;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
+ //Find node with max ASAP in current Set
+ MSchedGraphSBNode *node;
+ int maxASAP = 0;
+ DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
+ for(std::set<MSchedGraphSBNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
+ //Get node attributes
+ MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
+ //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
+
+ if(maxASAP <= nodeAttr.ASAP) {
+ maxASAP = nodeAttr.ASAP;
+ node = *J;
+ }
+ }
+ assert(node != 0 && "In node ordering node should not be null");
+ IntersectCurrent.insert(node);
+ order = BOTTOM_UP;
}
}
@@ -1481,138 +1481,138 @@
while(IntersectCurrent.size() > 0) {
if(order == TOP_DOWN) {
- DEBUG(std::cerr << "Order is TOP DOWN\n");
+ DEBUG(std::cerr << "Order is TOP DOWN\n");
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
-
- int MOB = 0;
- int height = 0;
- MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin());
-
- //Find node in intersection with highest heigh and lowest MOB
- for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
-
- //Get current nodes properties
- MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(height < nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- else if(height == nodeAttr.height) {
- if(MOB > nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
- //Append our node with greatest height to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
- FinalNodeOrder.push_back(highestHeightNode);
- }
-
- //Remove V from IntersectOrder
- IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
- IntersectCurrent.end(), highestHeightNode));
-
-
- //Intersect V's successors with CurrentSet
- for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(),
- E = highestHeightNode->succ_end(); P != E; ++P) {
- //if(lower_bound(CurrentSet->begin(),
- // CurrentSet->end(), *P) != CurrentSet->end()) {
- if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
- if(ignoreEdge(highestHeightNode, *P))
- continue;
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
- } //End while loop over Intersect Size
-
- //Change direction
- order = BOTTOM_UP;
-
- //Reset Intersect to reflect changes in OrderNodes
- IntersectCurrent.clear();
- predIntersect(*CurrentSet, IntersectCurrent);
-
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
+
+ int MOB = 0;
+ int height = 0;
+ MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin());
+
+ //Find node in intersection with highest heigh and lowest MOB
+ for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+
+ //Get current nodes properties
+ MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(height < nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ else if(height == nodeAttr.height) {
+ if(MOB > nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+ //Append our node with greatest height to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
+ FinalNodeOrder.push_back(highestHeightNode);
+ }
+
+ //Remove V from IntersectOrder
+ IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
+ IntersectCurrent.end(), highestHeightNode));
+
+
+ //Intersect V's successors with CurrentSet
+ for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(),
+ E = highestHeightNode->succ_end(); P != E; ++P) {
+ //if(lower_bound(CurrentSet->begin(),
+ // CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(ignoreEdge(highestHeightNode, *P))
+ continue;
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+ } //End while loop over Intersect Size
+
+ //Change direction
+ order = BOTTOM_UP;
+
+ //Reset Intersect to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ predIntersect(*CurrentSet, IntersectCurrent);
+
} //End If TOP_DOWN
-
- //Begin if BOTTOM_UP
+
+ //Begin if BOTTOM_UP
else {
- DEBUG(std::cerr << "Order is BOTTOM UP\n");
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
-
- //dump intersection
- DEBUG(dumpIntersection(IntersectCurrent));
- //Get node with highest depth, if a tie, use one with lowest
- //MOB
- int MOB = 0;
- int depth = 0;
- MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin());
-
- for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
- //Find node attribute in graph
- MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(depth < nodeAttr.depth) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- else if(depth == nodeAttr.depth) {
- if(MOB > nodeAttr.MOB) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
-
-
- //Append highest depth node to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
- FinalNodeOrder.push_back(highestDepthNode);
- }
- //Remove heightestDepthNode from IntersectOrder
- IntersectCurrent.erase(highestDepthNode);
-
-
- //Intersect heightDepthNode's pred with CurrentSet
- for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(),
- E = highestDepthNode->pred_end(); P != E; ++P) {
- if(CurrentSet->count(*P)) {
- if(ignoreEdge(*P, highestDepthNode))
- continue;
-
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
-
- } //End while loop over Intersect Size
-
- //Change order
- order = TOP_DOWN;
-
- //Reset IntersectCurrent to reflect changes in OrderNodes
- IntersectCurrent.clear();
- succIntersect(*CurrentSet, IntersectCurrent);
- } //End if BOTTOM_DOWN
-
+ DEBUG(std::cerr << "Order is BOTTOM UP\n");
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
+
+ //dump intersection
+ DEBUG(dumpIntersection(IntersectCurrent));
+ //Get node with highest depth, if a tie, use one with lowest
+ //MOB
+ int MOB = 0;
+ int depth = 0;
+ MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin());
+
+ for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+ //Find node attribute in graph
+ MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(depth < nodeAttr.depth) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ else if(depth == nodeAttr.depth) {
+ if(MOB > nodeAttr.MOB) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+
+
+ //Append highest depth node to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
+ FinalNodeOrder.push_back(highestDepthNode);
+ }
+ //Remove heightestDepthNode from IntersectOrder
+ IntersectCurrent.erase(highestDepthNode);
+
+
+ //Intersect heightDepthNode's pred with CurrentSet
+ for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(),
+ E = highestDepthNode->pred_end(); P != E; ++P) {
+ if(CurrentSet->count(*P)) {
+ if(ignoreEdge(*P, highestDepthNode))
+ continue;
+
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+
+ } //End while loop over Intersect Size
+
+ //Change order
+ order = TOP_DOWN;
+
+ //Reset IntersectCurrent to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ succIntersect(*CurrentSet, IntersectCurrent);
+ } //End if BOTTOM_DOWN
+
DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n");
}
//End Wrapping while loop
@@ -1638,15 +1638,15 @@
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphSBNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
- E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(*P,FinalNodeOrder[j]))
- continue;
-
+ continue;
+
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
@@ -1655,15 +1655,15 @@
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphSBNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
- E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(FinalNodeOrder[j],*P))
- continue;
+ continue;
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
@@ -1687,7 +1687,7 @@
//Loop over the final node order and process each node
for(std::vector<MSchedGraphSBNode*>::iterator I = FinalNodeOrder.begin(),
- E = FinalNodeOrder.end(); I != E; ++I) {
+ E = FinalNodeOrder.end(); I != E; ++I) {
//CalculateEarly and Late start
bool initialLSVal = false;
@@ -1699,59 +1699,59 @@
bool sched;
if((*I)->isBranch())
- if((*I)->hasPredecessors())
- sched = true;
- else
- sched = false;
+ if((*I)->hasPredecessors())
+ sched = true;
+ else
+ sched = false;
else
- sched = true;
+ sched = true;
if(sched) {
- //Loop over nodes in the schedule and determine if they are predecessors
- //or successors of the node we are trying to schedule
- for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
- nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
-
- //For this cycle, get the vector of nodes schedule and loop over it
- for(std::vector<MSchedGraphSBNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
-
- if((*I)->isPredecessor(*schedNode)) {
- int diff = (*I)->getInEdge(*schedNode).getIteDiff();
- int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- if(initialESVal)
- EarlyStart = std::max(EarlyStart, ES_Temp);
- else {
- EarlyStart = ES_Temp;
- initialESVal = true;
- }
- hasPred = true;
- }
- if((*I)->isSuccessor(*schedNode)) {
- int diff = (*schedNode)->getInEdge(*I).getIteDiff();
- int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- if(initialLSVal)
- LateStart = std::min(LateStart, LS_Temp);
- else {
- LateStart = LS_Temp;
- initialLSVal = true;
- }
- hasSucc = true;
- }
- }
- }
+ //Loop over nodes in the schedule and determine if they are predecessors
+ //or successors of the node we are trying to schedule
+ for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
+ nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
+
+ //For this cycle, get the vector of nodes schedule and loop over it
+ for(std::vector<MSchedGraphSBNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
+
+ if((*I)->isPredecessor(*schedNode)) {
+ int diff = (*I)->getInEdge(*schedNode).getIteDiff();
+ int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+ if(initialESVal)
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ else {
+ EarlyStart = ES_Temp;
+ initialESVal = true;
+ }
+ hasPred = true;
+ }
+ if((*I)->isSuccessor(*schedNode)) {
+ int diff = (*schedNode)->getInEdge(*I).getIteDiff();
+ int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+ if(initialLSVal)
+ LateStart = std::min(LateStart, LS_Temp);
+ else {
+ LateStart = LS_Temp;
+ initialLSVal = true;
+ }
+ hasSucc = true;
+ }
+ }
+ }
}
else {
- branches.push_back(*I);
- continue;
+ branches.push_back(*I);
+ continue;
}
//Check if the node has no pred or successors and set Early Start to its ASAP
if(!hasSucc && !hasPred)
- EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
+ EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n");
DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n");
@@ -1759,25 +1759,25 @@
//Now, try to schedule this node depending upon its pred and successor in the schedule
//already
if(!hasSucc && hasPred)
- success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
+ success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
else if(!hasPred && hasSucc)
- success = scheduleNode(*I, LateStart, (LateStart - II +1));
+ success = scheduleNode(*I, LateStart, (LateStart - II +1));
else if(hasPred && hasSucc) {
- if(EarlyStart > LateStart) {
- success = false;
- //LateStart = EarlyStart;
- DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
- }
- else
- success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
+ if(EarlyStart > LateStart) {
+ success = false;
+ //LateStart = EarlyStart;
+ DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
+ }
+ else
+ success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
}
else
- success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
+ success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
if(!success) {
- ++II;
- schedule.clear();
- break;
+ ++II;
+ schedule.clear();
+ break;
}
}
@@ -1787,8 +1787,8 @@
success = schedule.constructKernel(II, branches, indVarInstrs[SB]);
DEBUG(std::cerr << "Done Constructing Schedule Kernel\n");
if(!success) {
- ++II;
- schedule.clear();
+ ++II;
+ schedule.clear();
}
DEBUG(std::cerr << "Final II: " << II << "\n");
@@ -1806,7 +1806,7 @@
bool ModuloSchedulingSBPass::scheduleNode(MSchedGraphSBNode *node,
- int start, int end) {
+ int start, int end) {
bool success = false;
DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n");
@@ -1841,13 +1841,13 @@
++cycle;
DEBUG(std::cerr << "Increase cycle: " << cycle << "\n");
if(cycle > end)
- return false;
+ return false;
}
else {
--cycle;
DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n");
if(cycle < end)
- return false;
+ return false;
}
}
@@ -1885,46 +1885,46 @@
lastInstrs[inst] = I->second;
for(unsigned i=0; i < inst->getNumOperands(); ++i) {
- //get machine operand
- const MachineOperand &mOp = inst->getOperand(i);
-
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- if(isa<Constant>(srcI) || isa<Argument>(srcI))
- continue;
-
- //Before we declare this Value* one that we should save
- //make sure its def is not of the same stage as this instruction
- //because it will be consumed before its used
- Instruction *defInst = (Instruction*) srcI;
-
- //Should we save this value?
- bool save = true;
-
- //Continue if not in the def map, loop invariant code does not need to be saved
- if(!defMap.count(srcI))
- continue;
-
- MachineInstr *defInstr = defMap[srcI];
-
-
- if(lastInstrs.count(defInstr)) {
- if(lastInstrs[defInstr] == I->second) {
- save = false;
-
- }
- }
-
- if(save)
- valuesToSave[srcI] = std::make_pair(I->first, i);
- }
- }
-
- if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
- }
+ //get machine operand
+ const MachineOperand &mOp = inst->getOperand(i);
+
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ if(isa<Constant>(srcI) || isa<Argument>(srcI))
+ continue;
+
+ //Before we declare this Value* one that we should save
+ //make sure its def is not of the same stage as this instruction
+ //because it will be consumed before its used
+ Instruction *defInst = (Instruction*) srcI;
+
+ //Should we save this value?
+ bool save = true;
+
+ //Continue if not in the def map, loop invariant code does not need to be saved
+ if(!defMap.count(srcI))
+ continue;
+
+ MachineInstr *defInstr = defMap[srcI];
+
+
+ if(lastInstrs.count(defInstr)) {
+ if(lastInstrs[defInstr] == I->second) {
+ save = false;
+
+ }
+ }
+
+ if(save)
+ valuesToSave[srcI] = std::make_pair(I->first, i);
+ }
+ }
+
+ if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
+ }
}
}
@@ -1992,10 +1992,10 @@
//Print out epilogues and prologue
DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator PI = prologues.begin(), PE = prologues.end();
PI != PE; ++PI) {
- std::cerr << "PROLOGUE\n";
- for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
- (*I)->print(std::cerr);
- });
+ std::cerr << "PROLOGUE\n";
+ for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
+ (*I)->print(std::cerr);
+ });
DEBUG(std::cerr << "KERNEL\n");
DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);});
@@ -2014,10 +2014,10 @@
//Print out epilogues and prologue
DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator PI = prologues.begin(), PE = prologues.end();
PI != PE; ++PI) {
- std::cerr << "PROLOGUE\n";
- for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
- (*I)->print(std::cerr);
- });
+ std::cerr << "PROLOGUE\n";
+ for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
+ (*I)->print(std::cerr);
+ });
DEBUG(std::cerr << "KERNEL\n");
DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);});
@@ -2046,7 +2046,7 @@
bool sawFirst = false;
for(succ_iterator I = succ_begin(last),
- E = succ_end(last); I != E; ++I) {
+ E = succ_end(last); I != E; ++I) {
if (*I != SB[0]->getBasicBlock()) {
kernel_exit = *I;
break;
@@ -2066,71 +2066,71 @@
for(unsigned j = 0; j < prologues[i].size(); ++j) {
- MachineBasicBlock *currentMBB = prologues[i][j];
+ MachineBasicBlock *currentMBB = prologues[i][j];
- //Find terminator since getFirstTerminator does not work!
- for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
- MachineOpCode OC = mInst->getOpcode();
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we are branching to the kernel, if not branch to epilogue
- if(mOp.getVRegValue() == SB[0]->getBasicBlock()) {
- if(i >= prologues.size()-1)
- mOp.setValueReg(llvmKernelBB[0]);
- else
- mOp.setValueReg(llvm_prologues[i+1][0]);
- }
- else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) {
- mOp.setValueReg(llvm_epilogues[i][0]);
- }
- else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) {
- mOp.setValueReg(llvm_prologues[i][j+1]);
- }
-
- }
- }
-
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
- }
- }
-
- //Update llvm basic block with our new branch instr
- DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n");
-
- const BranchInst *branchVal = dyn_cast<BranchInst>(SB[i]->getBasicBlock()->getTerminator());
-
- //Check for inner branch
- if(j < prologues[i].size()-1) {
- //Find our side exit LLVM basic block
- BasicBlock *sideExit = 0;
- for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
- if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
- sideExit = branchVal->getSuccessor(s);
- }
- assert(sideExit && "Must have side exit llvm basic block");
- TerminatorInst *newBranch = new BranchInst(sideExit,
- llvm_prologues[i][j+1],
- branchVal->getCondition(),
- llvm_prologues[i][j]);
- }
- else {
- //If last prologue
- if(i == prologues.size()-1) {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
- llvm_epilogues[i][0],
- branchVal->getCondition(),
- llvm_prologues[i][j]);
- }
- else {
- TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0],
- llvm_epilogues[i][0],
- branchVal->getCondition(),
- llvm_prologues[i][j]);
- }
- }
+ //Find terminator since getFirstTerminator does not work!
+ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+ MachineOpCode OC = mInst->getOpcode();
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we are branching to the kernel, if not branch to epilogue
+ if(mOp.getVRegValue() == SB[0]->getBasicBlock()) {
+ if(i >= prologues.size()-1)
+ mOp.setValueReg(llvmKernelBB[0]);
+ else
+ mOp.setValueReg(llvm_prologues[i+1][0]);
+ }
+ else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) {
+ mOp.setValueReg(llvm_epilogues[i][0]);
+ }
+ else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) {
+ mOp.setValueReg(llvm_prologues[i][j+1]);
+ }
+
+ }
+ }
+
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ }
+ }
+
+ //Update llvm basic block with our new branch instr
+ DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n");
+
+ const BranchInst *branchVal = dyn_cast<BranchInst>(SB[i]->getBasicBlock()->getTerminator());
+
+ //Check for inner branch
+ if(j < prologues[i].size()-1) {
+ //Find our side exit LLVM basic block
+ BasicBlock *sideExit = 0;
+ for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
+ if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
+ sideExit = branchVal->getSuccessor(s);
+ }
+ assert(sideExit && "Must have side exit llvm basic block");
+ TerminatorInst *newBranch = new BranchInst(sideExit,
+ llvm_prologues[i][j+1],
+ branchVal->getCondition(),
+ llvm_prologues[i][j]);
+ }
+ else {
+ //If last prologue
+ if(i == prologues.size()-1) {
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+ llvm_epilogues[i][0],
+ branchVal->getCondition(),
+ llvm_prologues[i][j]);
+ }
+ else {
+ TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0],
+ llvm_epilogues[i][0],
+ branchVal->getCondition(),
+ llvm_prologues[i][j]);
+ }
+ }
}
}
}
@@ -2142,29 +2142,29 @@
for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
MachineOpCode OC = mInst->getOpcode();
if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
-
- if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Deal with inner kernel branches
- if(i < machineKernelBB.size()-1) {
- if(mOp.getVRegValue() == SB[i+1]->getBasicBlock())
- mOp.setValueReg(llvmKernelBB[i+1]);
- //Side exit!
- else {
- sideExits[SB[i]] = mOp.getVRegValue();
- }
- }
- else {
- if(mOp.getVRegValue() == SB[0]->getBasicBlock())
- mOp.setValueReg(llvmKernelBB[0]);
- else {
- if(llvm_epilogues.size() > 0)
- mOp.setValueReg(llvm_epilogues[0][0]);
- }
- }
- }
- }
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+
+ if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Deal with inner kernel branches
+ if(i < machineKernelBB.size()-1) {
+ if(mOp.getVRegValue() == SB[i+1]->getBasicBlock())
+ mOp.setValueReg(llvmKernelBB[i+1]);
+ //Side exit!
+ else {
+ sideExits[SB[i]] = mOp.getVRegValue();
+ }
+ }
+ else {
+ if(mOp.getVRegValue() == SB[0]->getBasicBlock())
+ mOp.setValueReg(llvmKernelBB[0]);
+ else {
+ if(llvm_epilogues.size() > 0)
+ mOp.setValueReg(llvm_epilogues[0][0]);
+ }
+ }
+ }
+ }
}
}
@@ -2177,28 +2177,28 @@
//Find our side exit LLVM basic block
BasicBlock *sideExit = 0;
for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
- if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
- sideExit = branchVal->getSuccessor(s);
+ if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
+ sideExit = branchVal->getSuccessor(s);
}
assert(sideExit && "Must have side exit llvm basic block");
TerminatorInst *newBranch = new BranchInst(sideExit,
- llvmKernelBB[i+1],
- branchVal->getCondition(),
- llvmKernelBB[i]);
+ llvmKernelBB[i+1],
+ branchVal->getCondition(),
+ llvmKernelBB[i]);
}
else {
//Deal with outter branches
if(epilogues.size() > 0) {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
- llvm_epilogues[0][0],
- branchVal->getCondition(),
- llvmKernelBB[i]);
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+ llvm_epilogues[0][0],
+ branchVal->getCondition(),
+ llvmKernelBB[i]);
}
else {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
- kernel_exit,
- branchVal->getCondition(),
- llvmKernelBB[i]);
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+ kernel_exit,
+ branchVal->getCondition(),
+ llvmKernelBB[i]);
}
}
}
@@ -2209,73 +2209,73 @@
for(unsigned i = 0; i < epilogues.size(); ++i) {
for(unsigned j=0; j < epilogues[i].size(); ++j) {
- //Now since we don't have fall throughs, add a unconditional
- //branch to the next prologue
-
- //Before adding these, we need to check if the epilogue already has
- //a branch in it
- bool hasBranch = false;
- /*if(j < epilogues[i].size()-1) {
- MachineBasicBlock *currentMBB = epilogues[i][j];
- for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
-
- MachineOpCode OC = mInst->getOpcode();
-
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- hasBranch = true;
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
-
- if(mOp.getVRegValue() != sideExits[SB[j]]) {
- mOp.setValueReg(llvm_epilogues[i][j+1]);
- }
-
- }
- }
-
-
- DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n");
- }
- }
- if(hasBranch) {
- const BranchInst *branchVal = dyn_cast<BranchInst>(SB[j]->getBasicBlock()->getTerminator());
- TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]],
- llvm_epilogues[i][j+1],
- branchVal->getCondition(),
- llvm_epilogues[i][j]);
- }
- }*/
-
- if(!hasBranch) {
-
- //Handle inner branches
- if(j < epilogues[i].size()-1) {
- BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]);
- TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1],
- llvm_epilogues[i][j]);
- }
- else {
-
- //Check if this is the last epilogue
- if(i != epilogues.size()-1) {
- BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]);
- //Add unconditional branch to end of epilogue
- TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0],
- llvm_epilogues[i][j]);
-
- }
- else {
- BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit);
- TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]);
- }
- }
-
- //Add one more nop!
- BuildMI(epilogues[i][j], V9::NOP, 0);
-
- }
+ //Now since we don't have fall throughs, add a unconditional
+ //branch to the next prologue
+
+ //Before adding these, we need to check if the epilogue already has
+ //a branch in it
+ bool hasBranch = false;
+ /*if(j < epilogues[i].size()-1) {
+ MachineBasicBlock *currentMBB = epilogues[i][j];
+ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+
+ MachineOpCode OC = mInst->getOpcode();
+
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ hasBranch = true;
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+
+ if(mOp.getVRegValue() != sideExits[SB[j]]) {
+ mOp.setValueReg(llvm_epilogues[i][j+1]);
+ }
+
+ }
+ }
+
+
+ DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n");
+ }
+ }
+ if(hasBranch) {
+ const BranchInst *branchVal = dyn_cast<BranchInst>(SB[j]->getBasicBlock()->getTerminator());
+ TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]],
+ llvm_epilogues[i][j+1],
+ branchVal->getCondition(),
+ llvm_epilogues[i][j]);
+ }
+ }*/
+
+ if(!hasBranch) {
+
+ //Handle inner branches
+ if(j < epilogues[i].size()-1) {
+ BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]);
+ TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1],
+ llvm_epilogues[i][j]);
+ }
+ else {
+
+ //Check if this is the last epilogue
+ if(i != epilogues.size()-1) {
+ BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]);
+ //Add unconditional branch to end of epilogue
+ TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0],
+ llvm_epilogues[i][j]);
+
+ }
+ else {
+ BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit);
+ TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]);
+ }
+ }
+
+ //Add one more nop!
+ BuildMI(epilogues[i][j], V9::NOP, 0);
+
+ }
}
}
}
@@ -2287,7 +2287,7 @@
std::vector<const BasicBlock*>Preds (pred_begin(llvmBB), pred_end(llvmBB));
for(std::vector<const BasicBlock*>::iterator P = Preds.begin(),
- PE = Preds.end(); P != PE; ++P) {
+ PE = Preds.end(); P != PE; ++P) {
if(*P == SB[SB.size()-1]->getBasicBlock())
continue;
else {
@@ -2299,55 +2299,55 @@
//Update the terminator
TerminatorInst *term = ((BasicBlock*)*P)->getTerminator();
for(unsigned i=0; i < term->getNumSuccessors(); ++i) {
- if(term->getSuccessor(i) == llvmBB) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- if(llvm_prologues.size() > 0) {
- term->setSuccessor(i, llvm_prologues[0][0]);
-
- DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n");
-
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvm_prologues[0][0]);
- }
- }
- }
- }
- }
- else {
- term->setSuccessor(i, llvmKernelBB[0]);
-
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for(unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvmKernelBB[0]);
- }
- }
- }
- }
- }
- }
+ if(term->getSuccessor(i) == llvmBB) {
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ if(llvm_prologues.size() > 0) {
+ term->setSuccessor(i, llvm_prologues[0][0]);
+
+ DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n");
+
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvm_prologues[0][0]);
+ }
+ }
+ }
+ }
+ }
+ else {
+ term->setSuccessor(i, llvmKernelBB[0]);
+
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for(unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvmKernelBB[0]);
+ }
+ }
+ }
+ }
+ }
+ }
}
break;
}
@@ -2384,7 +2384,7 @@
std::vector<BasicBlock*> current_llvm_prologue;
for(std::vector<const MachineBasicBlock*>::iterator MB = origSB.begin(),
- MBE = origSB.end(); MB != MBE; ++MB) {
+ MBE = origSB.end(); MB != MBE; ++MB) {
const MachineBasicBlock *MBB = *MB;
//Create new llvm and machine bb
BasicBlock *llvmBB = new BasicBlock("PROLOGUE", (Function*) (MBB->getBasicBlock()->getParent()));
@@ -2393,91 +2393,91 @@
DEBUG(std::cerr << "i=" << i << "\n");
for(int j = i; j >= 0; --j) {
- //iterate over instructions in original bb
- for(MachineBasicBlock::const_iterator MI = MBB->begin(),
- ME = MBB->end(); ME != MI; ++MI) {
- if(inKernel[j].count(&*MI)) {
- MachineInstr *instClone = MI->clone();
- machineBB->push_back(instClone);
-
- //If its a branch, insert a nop
- if(mii->isBranch(instClone->getOpcode()))
- BuildMI(machineBB, V9::NOP, 0);
-
-
- DEBUG(std::cerr << "Cloning: " << *MI << "\n");
-
- //After cloning, we may need to save the value that this instruction defines
- for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
- Instruction *tmp;
-
- //get machine operand
- MachineOperand &mOp = instClone->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- && mOp.isDef()) {
-
- //Check if this is a value we should save
- if(valuesToSave.count(mOp.getVRegValue())) {
- //Save copy in tmpInstruction
- tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Add TmpInstruction to safe LLVM Instruction MCFI
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue())
- << " New Value: " << *tmp << " Stage: " << i << "\n");
-
- newValues[mOp.getVRegValue()][i]= tmp;
- newValLocation[tmp] = machineBB;
-
- DEBUG(std::cerr << "Machine Instr Operands: "
- << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
-
- //Create machine instruction and put int machineBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
- }
- }
-
- //We may also need to update the value that we use if
- //its from an earlier prologue
- if(j != 0) {
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i-1)) {
- Value *oldV = mOp.getVRegValue();
- DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
- //Update the operand with the right value
- mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
-
- //Remove this value since we have consumed it
- //NOTE: Should this only be done if j != maxStage?
- consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
- DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
- newValues[oldV].erase(i-1);
- }
- }
- else
- if(consumedValues.count(mOp.getVRegValue()))
- assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
- }
- }
- }
- }
- }
- }
- (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
- current_prologue.push_back(machineBB);
- current_llvm_prologue.push_back(llvmBB);
+ //iterate over instructions in original bb
+ for(MachineBasicBlock::const_iterator MI = MBB->begin(),
+ ME = MBB->end(); ME != MI; ++MI) {
+ if(inKernel[j].count(&*MI)) {
+ MachineInstr *instClone = MI->clone();
+ machineBB->push_back(instClone);
+
+ //If its a branch, insert a nop
+ if(mii->isBranch(instClone->getOpcode()))
+ BuildMI(machineBB, V9::NOP, 0);
+
+
+ DEBUG(std::cerr << "Cloning: " << *MI << "\n");
+
+ //After cloning, we may need to save the value that this instruction defines
+ for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
+ Instruction *tmp;
+
+ //get machine operand
+ MachineOperand &mOp = instClone->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ && mOp.isDef()) {
+
+ //Check if this is a value we should save
+ if(valuesToSave.count(mOp.getVRegValue())) {
+ //Save copy in tmpInstruction
+ tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Add TmpInstruction to safe LLVM Instruction MCFI
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue())
+ << " New Value: " << *tmp << " Stage: " << i << "\n");
+
+ newValues[mOp.getVRegValue()][i]= tmp;
+ newValLocation[tmp] = machineBB;
+
+ DEBUG(std::cerr << "Machine Instr Operands: "
+ << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
+
+ //Create machine instruction and put int machineBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
+ }
+ }
+
+ //We may also need to update the value that we use if
+ //its from an earlier prologue
+ if(j != 0) {
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i-1)) {
+ Value *oldV = mOp.getVRegValue();
+ DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
+ //Update the operand with the right value
+ mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
+
+ //Remove this value since we have consumed it
+ //NOTE: Should this only be done if j != maxStage?
+ consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
+ DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
+ newValues[oldV].erase(i-1);
+ }
+ }
+ else
+ if(consumedValues.count(mOp.getVRegValue()))
+ assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
+ }
+ }
+ }
+ }
+ }
+ }
+ (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
+ current_prologue.push_back(machineBB);
+ current_llvm_prologue.push_back(llvmBB);
}
prologues.push_back(current_prologue);
llvm_prologues.push_back(current_llvm_prologue);
@@ -2523,58 +2523,58 @@
std::map<Value*, int> inEpilogue;
for(MachineBasicBlock::const_iterator MI = MBB->begin(), ME = MBB->end(); ME != MI; ++MI) {
- for(int j=schedule.getMaxStage(); j > i; --j) {
- if(inKernel[j].count(&*MI)) {
- DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
- MachineInstr *clone = MI->clone();
-
- //Update operands that need to use the result from the phi
- for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
- //get machine operand
- const MachineOperand &mOp = clone->getOperand(opNum);
-
- if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
-
- DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
-
- //If this is the last instructions for the max iterations ago, don't update operands
- if(inEpilogue.count(mOp.getVRegValue()))
- if(inEpilogue[mOp.getVRegValue()] == i)
- continue;
-
- //Quickly write appropriate phis for this operand
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i)) {
- Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //assert of no kernelPHI for this value
- assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
-
- MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- valPHIs[mOp.getVRegValue()] = tmp;
- }
- }
-
- if(valPHIs.count(mOp.getVRegValue())) {
- //Update the operand in the cloned instruction
- clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
- }
- }
- else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
- inEpilogue[mOp.getVRegValue()] = i;
- }
-
- }
- machineBB->push_back(clone);
- //if(MTI->isBranch(clone->getOpcode()))
- //BuildMI(machineBB, V9::NOP, 0);
- }
- }
+ for(int j=schedule.getMaxStage(); j > i; --j) {
+ if(inKernel[j].count(&*MI)) {
+ DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
+ MachineInstr *clone = MI->clone();
+
+ //Update operands that need to use the result from the phi
+ for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
+ //get machine operand
+ const MachineOperand &mOp = clone->getOperand(opNum);
+
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
+
+ DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
+
+ //If this is the last instructions for the max iterations ago, don't update operands
+ if(inEpilogue.count(mOp.getVRegValue()))
+ if(inEpilogue[mOp.getVRegValue()] == i)
+ continue;
+
+ //Quickly write appropriate phis for this operand
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i)) {
+ Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //assert of no kernelPHI for this value
+ assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
+
+ MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ valPHIs[mOp.getVRegValue()] = tmp;
+ }
+ }
+
+ if(valPHIs.count(mOp.getVRegValue())) {
+ //Update the operand in the cloned instruction
+ clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
+ }
+ }
+ else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
+ inEpilogue[mOp.getVRegValue()] = i;
+ }
+
+ }
+ machineBB->push_back(clone);
+ //if(MTI->isBranch(clone->getOpcode()))
+ //BuildMI(machineBB, V9::NOP, 0);
+ }
+ }
}
(((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
current_epilogue.push_back(machineBB);
@@ -2583,7 +2583,7 @@
DEBUG(std::cerr << "EPILOGUE #" << i << "\n");
DEBUG(for(std::vector<MachineBasicBlock*>::iterator B = current_epilogue.begin(), BE = current_epilogue.end(); B != BE; ++B) {
- (*B)->print(std::cerr);});
+ (*B)->print(std::cerr);});
epilogues.push_back(current_epilogue);
llvm_epilogues.push_back(current_llvm_epilogue);
@@ -2646,64 +2646,64 @@
if(I->second != 0) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //Check to see where this operand is defined if this instruction is from max stage
- if(I->second == schedule.getMaxStage()) {
- DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
- }
-
- //If its in the value saved, we need to create a temp instruction and use that instead
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- //Check if we already have a final PHI value for this
- if(!finalPHIValue.count(mOp.getVRegValue())) {
- //Only create phi if the operand def is from a stage before this one
- if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //Update the operand in the cloned instruction
- instClone->getOperand(i).setValueReg(tmp);
-
- //save this as our final phi
- finalPHIValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB[index];
- }
- }
- else {
- //Use the previous final phi value
- instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
- }
- }
+ //Check to see where this operand is defined if this instruction is from max stage
+ if(I->second == schedule.getMaxStage()) {
+ DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
+ }
+
+ //If its in the value saved, we need to create a temp instruction and use that instead
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ //Check if we already have a final PHI value for this
+ if(!finalPHIValue.count(mOp.getVRegValue())) {
+ //Only create phi if the operand def is from a stage before this one
+ if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //Update the operand in the cloned instruction
+ instClone->getOperand(i).setValueReg(tmp);
+
+ //save this as our final phi
+ finalPHIValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB[index];
+ }
+ }
+ else {
+ //Use the previous final phi value
+ instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
+ }
+ }
}
}
if(I->second != schedule.getMaxStage()) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
- tempVec.addTemp((Value*) tmp);
-
- //Create new machine instr and put in MBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- //Save for future cleanup
- kernelValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB[index];
- kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
- }
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
+ tempVec.addTemp((Value*) tmp);
+
+ //Create new machine instr and put in MBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ //Save for future cleanup
+ kernelValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB[index];
+ kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
+ }
}
}
}
@@ -2718,7 +2718,7 @@
DEBUG(std::cerr << "Writing phi for" << *(V->first));
DEBUG(std::cerr << "\nMap of Value* for this phi\n");
DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
- IE = V->second.end(); I != IE; ++I) {
+ IE = V->second.end(); I != IE; ++I) {
std::cerr << "Stage: " << I->first;
std::cerr << " Value: " << *(I->second) << "\n";
});
@@ -2740,42 +2740,42 @@
unsigned count = 1;
//Loop over the the map backwards to generate phis
for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
- I != IE; ++I) {
+ I != IE; ++I) {
if(count < (V->second).size()) {
- if(lastPhi == 0) {
- lastPhi = new TmpInstruction(I->second);
+ if(lastPhi == 0) {
+ lastPhi = new TmpInstruction(I->second);
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) lastPhi);
-
- MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- newValLocation[lastPhi] = machineBB[0];
- }
- else {
- Instruction *tmp = new TmpInstruction(I->second);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
-
- MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- lastPhi = tmp;
- kernelPHIs[V->first][I->first] = lastPhi;
- newValLocation[lastPhi] = machineBB[0];
- }
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) lastPhi);
+
+ MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ newValLocation[lastPhi] = machineBB[0];
+ }
+ else {
+ Instruction *tmp = new TmpInstruction(I->second);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+
+ MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ lastPhi = tmp;
+ kernelPHIs[V->first][I->first] = lastPhi;
+ newValLocation[lastPhi] = machineBB[0];
+ }
}
//Final phi value
else {
- //The resulting value must be the Value* we created earlier
- assert(lastPhi != 0 && "Last phi is NULL!\n");
- MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
+ //The resulting value must be the Value* we created earlier
+ assert(lastPhi != 0 && "Last phi is NULL!\n");
+ MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
}
++count;
@@ -2814,58 +2814,58 @@
Instruction *tmp = 0;
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
-
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister
- && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new
- //TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
- if(tmp->getType() == Type::FloatTy)
- BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
-
- worklist.push_back(std::make_pair(kernelBB[0], I));
- }
-
+
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister
+ && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new
+ //TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+
+ worklist.push_back(std::make_pair(kernelBB[0], I));
+ }
+
}
}
@@ -2885,68 +2885,68 @@
//Remove phis from epilogue
for(std::vector<std::vector<MachineBasicBlock*> >::iterator MB = epilogues.begin(),
- ME = epilogues.end(); MB != ME; ++MB) {
+ ME = epilogues.end(); MB != ME; ++MB) {
for(std::vector<MachineBasicBlock*>::iterator currentMBB = MB->begin(), currentME = MB->end(); currentMBB != currentME; ++currentMBB) {
for(MachineBasicBlock::iterator I = (*currentMBB)->begin(),
- E = (*currentMBB)->end(); I != E; ++I) {
+ E = (*currentMBB)->end(); I != E; ++I) {
- DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
- //Get op code and check if its a phi
- if(I->getOpcode() == V9::PHI) {
- Instruction *tmp = 0;
-
- for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- if(tmp->getType() == Type::FloatTy)
- BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
- worklist.push_back(std::make_pair(*currentMBB,I));
- }
- }
- }
+ DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
+ //Get op code and check if its a phi
+ if(I->getOpcode() == V9::PHI) {
+ Instruction *tmp = 0;
+
+ for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+ worklist.push_back(std::make_pair(*currentMBB,I));
+ }
+ }
+ }
}
}
}
@@ -2964,7 +2964,7 @@
for(std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) {
DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
I->first->erase(I->second);
-
+
}
@@ -3001,8 +3001,8 @@
if(instrsMovedDown.count(mbb)) {
for(std::vector<std::pair<MachineInstr*, int> >::iterator I = instrsMovedDown[mbb].begin(), E = instrsMovedDown[mbb].end(); I != E; ++I) {
- if(branchStage[mbb] == I->second)
- sideMBB->push_back((I->first)->clone());
+ if(branchStage[mbb] == I->second)
+ sideMBB->push_back((I->first)->clone());
}
//Add unconditional branches to original exits
@@ -3024,36 +3024,36 @@
std::vector<BasicBlock*> newLLVMEp;
for(std::vector<MachineBasicBlock*>::iterator currentMBB = MB.begin(),
- lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) {
- BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent());
- MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB);
-
- //Clone instructions and insert into new MBB
- for(MachineBasicBlock::iterator I = (*currentMBB)->begin(),
- E = (*currentMBB)->end(); I != E; ++I) {
-
- MachineInstr *clone = I->clone();
- if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) {
- //update branch to side exit
- for(unsigned i = 0; i < clone->getNumOperands(); ++i) {
- MachineOperand &mOp = clone->getOperand(i);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- mOp.setValueReg(sideBB);
- }
- }
- }
-
- tmp->push_back(clone);
-
- }
+ lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) {
+ BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent());
+ MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB);
+
+ //Clone instructions and insert into new MBB
+ for(MachineBasicBlock::iterator I = (*currentMBB)->begin(),
+ E = (*currentMBB)->end(); I != E; ++I) {
+
+ MachineInstr *clone = I->clone();
+ if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) {
+ //update branch to side exit
+ for(unsigned i = 0; i < clone->getNumOperands(); ++i) {
+ MachineOperand &mOp = clone->getOperand(i);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ mOp.setValueReg(sideBB);
+ }
+ }
+ }
+
+ tmp->push_back(clone);
+
+ }
- //Add llvm branch
- TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB);
+ //Add llvm branch
+ TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB);
- newEp.push_back(tmp);
- (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp);
+ newEp.push_back(tmp);
+ (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp);
- newLLVMEp.push_back(tmpBB);
+ newLLVMEp.push_back(tmpBB);
}
side_llvm_epilogues.push_back(newLLVMEp);
@@ -3069,44 +3069,44 @@
//Get BB side exit we are dealing with
MachineBasicBlock *currentMBB = prologues[P][sideExitNum];
if(P >= (unsigned) stage) {
- //Iterate backwards of machine instructions to find the branch we need to update
- for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
- MachineOpCode OC = mInst->getOpcode();
-
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we branch to side exit
- if(mOp.getVRegValue() == sideExits[mbb]) {
- mOp.setValueReg(side_llvm_epilogues[P][0]);
- }
- }
- }
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
- }
- }
-
- //Update llvm branch
- TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator();
- DEBUG(std::cerr << *branchVal << "\n");
-
- for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
- if(branchVal->getSuccessor(i) == sideExits[mbb]) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- branchVal->setSuccessor(i, side_llvm_epilogues[P][0]);
- }
- }
+ //Iterate backwards of machine instructions to find the branch we need to update
+ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+ MachineOpCode OC = mInst->getOpcode();
+
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we branch to side exit
+ if(mOp.getVRegValue() == sideExits[mbb]) {
+ mOp.setValueReg(side_llvm_epilogues[P][0]);
+ }
+ }
+ }
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ }
+ }
+
+ //Update llvm branch
+ TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator();
+ DEBUG(std::cerr << *branchVal << "\n");
+
+ for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
+ if(branchVal->getSuccessor(i) == sideExits[mbb]) {
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ branchVal->setSuccessor(i, side_llvm_epilogues[P][0]);
+ }
+ }
}
else {
- //must add BA branch because another prologue or kernel has the actual side exit branch
- //Add unconditional branches to original exits
- assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to");
- BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock());
- BuildMI(prologues[P][sideExitNum], V9::NOP, 0);
+ //must add BA branch because another prologue or kernel has the actual side exit branch
+ //Add unconditional branches to original exits
+ assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to");
+ BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock());
+ BuildMI(prologues[P][sideExitNum], V9::NOP, 0);
- TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock());
+ TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock());
}
}
@@ -3120,19 +3120,19 @@
//If its a branch update its branchto
if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we branch to side exit
- if(mOp.getVRegValue() == sideExits[mbb]) {
- if(side_llvm_epilogues.size() > 0)
- mOp.setValueReg(side_llvm_epilogues[0][0]);
- else
- mOp.setValueReg(sideBB);
- }
- }
- }
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we branch to side exit
+ if(mOp.getVRegValue() == sideExits[mbb]) {
+ if(side_llvm_epilogues.size() > 0)
+ mOp.setValueReg(side_llvm_epilogues[0][0]);
+ else
+ mOp.setValueReg(sideBB);
+ }
+ }
+ }
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
}
}
@@ -3143,11 +3143,11 @@
for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
if(branchVal->getSuccessor(i) == sideExits[mbb]) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- if(side_llvm_epilogues.size() > 0)
- branchVal->setSuccessor(i, side_llvm_epilogues[0][0]);
- else
- branchVal->setSuccessor(i, sideBB);
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ if(side_llvm_epilogues.size() > 0)
+ branchVal->setSuccessor(i, side_llvm_epilogues[0][0]);
+ else
+ branchVal->setSuccessor(i, sideBB);
}
}
}
Index: llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h
diff -u llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.2 llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.3
--- llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h:1.2 Thu Jun 16 23:00:57 2005
+++ llvm/lib/Target/SparcV9/ModuloScheduling/ModuloSchedulingSuperBlock.h Wed Jul 27 00:53:44 2005
@@ -33,9 +33,9 @@
int depth;
int height;
MSNodeSBAttributes(int asap=-1, int alap=-1, int mob=-1,
- int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
- MOB(mob), depth(d),
- height(h) {}
+ int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
+ MOB(mob), depth(d),
+ height(h) {}
};
@@ -43,7 +43,7 @@
class ModuloSchedulingSBPass : public FunctionPass {
const TargetMachine ⌖
-
+
//Map to hold Value* defs
std::map<const Value*, MachineInstr*> defMap;
@@ -52,7 +52,7 @@
//Map to hold machine to llvm instrs for each valid BB
std::map<SuperBlock, std::map<MachineInstr*, Instruction*> > machineTollvm;
-
+
//LLVM Instruction we know we can add TmpInstructions to its MCFI
Instruction *defaultInst;
@@ -76,116 +76,116 @@
//Current initiation interval
int II;
-
+
//Internal Functions
- void FindSuperBlocks(Function &F, LoopInfo &LI,
- std::vector<std::vector<const MachineBasicBlock*> > &Worklist);
+ void FindSuperBlocks(Function &F, LoopInfo &LI,
+ std::vector<std::vector<const MachineBasicBlock*> > &Worklist);
bool MachineBBisValid(const MachineBasicBlock *B,
- std::map<const MachineInstr*, unsigned> &indexMap,
- unsigned &offset);
+ std::map<const MachineInstr*, unsigned> &indexMap,
+ unsigned &offset);
bool CreateDefMap(std::vector<const MachineBasicBlock*> &SB);
- bool getIndVar(std::vector<const MachineBasicBlock*> &superBlock,
- std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- std::map<const MachineInstr*, unsigned> &indexMap);
+ bool getIndVar(std::vector<const MachineBasicBlock*> &superBlock,
+ std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+ std::map<const MachineInstr*, unsigned> &indexMap);
bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack,
- std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- const BasicBlock *first,
- std::set<const BasicBlock*> &llvmSuperBlock);
+ std::vector<Instruction*> &stack,
+ std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+ const BasicBlock *first,
+ std::set<const BasicBlock*> &llvmSuperBlock);
int calculateResMII(std::vector<const MachineBasicBlock*> &superBlock);
int calculateRecMII(MSchedGraphSB *graph, int MII);
void findAllCircuits(MSchedGraphSB *g, int II);
- void addRecc(std::vector<MSchedGraphSBNode*> &stack,
- std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+ void addRecc(std::vector<MSchedGraphSBNode*> &stack,
+ std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
bool circuit(MSchedGraphSBNode *v, std::vector<MSchedGraphSBNode*> &stack,
- std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
- MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*,
- std::set<MSchedGraphSBNode*> > &B,
- int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+ std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
+ MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*,
+ std::set<MSchedGraphSBNode*> > &B,
+ int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
void unblock(MSchedGraphSBNode *u, std::set<MSchedGraphSBNode*> &blocked,
- std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B);
+ std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B);
void addSCC(std::vector<MSchedGraphSBNode*> &SCC, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
void calculateNodeAttributes(MSchedGraphSB *graph, int MII);
bool ignoreEdge(MSchedGraphSBNode *srcNode, MSchedGraphSBNode *destNode);
int calculateASAP(MSchedGraphSBNode *node, int MII, MSchedGraphSBNode *destNode);
int calculateALAP(MSchedGraphSBNode *node, int MII,
- int maxASAP, MSchedGraphSBNode *srcNode);
+ int maxASAP, MSchedGraphSBNode *srcNode);
int findMaxASAP();
int calculateHeight(MSchedGraphSBNode *node,MSchedGraphSBNode *srcNode);
int calculateDepth(MSchedGraphSBNode *node, MSchedGraphSBNode *destNode);
void computePartialOrder();
- void connectedComponentSet(MSchedGraphSBNode *node, std::set<MSchedGraphSBNode*> &ccSet,
- std::set<MSchedGraphSBNode*> &lastNodes);
+ void connectedComponentSet(MSchedGraphSBNode *node, std::set<MSchedGraphSBNode*> &ccSet,
+ std::set<MSchedGraphSBNode*> &lastNodes);
void searchPath(MSchedGraphSBNode *node,
- std::vector<MSchedGraphSBNode*> &path,
- std::set<MSchedGraphSBNode*> &nodesToAdd,
- std::set<MSchedGraphSBNode*> &new_reccurrence);
+ std::vector<MSchedGraphSBNode*> &path,
+ std::set<MSchedGraphSBNode*> &nodesToAdd,
+ std::set<MSchedGraphSBNode*> &new_reccurrence);
void orderNodes();
bool computeSchedule(std::vector<const MachineBasicBlock*> &BB, MSchedGraphSB *MSG);
bool scheduleNode(MSchedGraphSBNode *node, int start, int end);
void predIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult);
void succIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult);
void reconstructLoop(std::vector<const MachineBasicBlock*> &SB);
- void fixBranches(std::vector<std::vector<MachineBasicBlock*> > &prologues,
- std::vector<std::vector<BasicBlock*> > &llvm_prologues,
- std::vector<MachineBasicBlock*> &machineKernelBB,
- std::vector<BasicBlock*> &llvmKernelBB,
- std::vector<std::vector<MachineBasicBlock*> > &epilogues,
- std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
- std::vector<const MachineBasicBlock*> &SB,
- std::map<const MachineBasicBlock*, Value*> &sideExits);
-
- void writePrologues(std::vector<std::vector<MachineBasicBlock *> > &prologues,
- std::vector<const MachineBasicBlock*> &origBB,
- std::vector<std::vector<BasicBlock*> > &llvm_prologues,
- std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
- std::map<Value*, std::map<int, Value*> > &newValues,
- std::map<Value*, MachineBasicBlock*> &newValLocation);
-
- void writeKernel(std::vector<BasicBlock*> &llvmBB, std::vector<MachineBasicBlock*> &machineBB,
- std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
- std::map<Value*, std::map<int, Value*> > &newValues,
- std::map<Value*, MachineBasicBlock*> &newValLocation,
- std::map<Value*, std::map<int, Value*> > &kernelPHIs);
-
- void removePHIs(std::vector<const MachineBasicBlock*> &SB,
- std::vector<std::vector<MachineBasicBlock*> > &prologues,
- std::vector<std::vector<MachineBasicBlock*> > &epilogues,
- std::vector<MachineBasicBlock*> &kernelBB,
- std::map<Value*, MachineBasicBlock*> &newValLocation);
-
- void writeEpilogues(std::vector<std::vector<MachineBasicBlock*> > &epilogues,
- std::vector<const MachineBasicBlock*> &origSB,
- std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
- std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
- std::map<Value*, std::map<int, Value*> > &newValues,
- std::map<Value*, MachineBasicBlock*> &newValLocation,
- std::map<Value*, std::map<int, Value*> > &kernelPHIs);
-
- void writeSideExits(std::vector<std::vector<MachineBasicBlock *> > &prologues,
- std::vector<std::vector<BasicBlock*> > &llvm_prologues,
- std::vector<std::vector<MachineBasicBlock *> > &epilogues,
- std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
- std::map<const MachineBasicBlock*, Value*> &sideExits,
- std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > &instrsMovedDown,
- std::vector<const MachineBasicBlock*> &SB,
- std::vector<MachineBasicBlock*> &kernelMBBs,
- std::map<MachineBasicBlock*, int> branchStage);
+ void fixBranches(std::vector<std::vector<MachineBasicBlock*> > &prologues,
+ std::vector<std::vector<BasicBlock*> > &llvm_prologues,
+ std::vector<MachineBasicBlock*> &machineKernelBB,
+ std::vector<BasicBlock*> &llvmKernelBB,
+ std::vector<std::vector<MachineBasicBlock*> > &epilogues,
+ std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
+ std::vector<const MachineBasicBlock*> &SB,
+ std::map<const MachineBasicBlock*, Value*> &sideExits);
+
+ void writePrologues(std::vector<std::vector<MachineBasicBlock *> > &prologues,
+ std::vector<const MachineBasicBlock*> &origBB,
+ std::vector<std::vector<BasicBlock*> > &llvm_prologues,
+ std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+ std::map<Value*, std::map<int, Value*> > &newValues,
+ std::map<Value*, MachineBasicBlock*> &newValLocation);
+
+ void writeKernel(std::vector<BasicBlock*> &llvmBB, std::vector<MachineBasicBlock*> &machineBB,
+ std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+ std::map<Value*, std::map<int, Value*> > &newValues,
+ std::map<Value*, MachineBasicBlock*> &newValLocation,
+ std::map<Value*, std::map<int, Value*> > &kernelPHIs);
+
+ void removePHIs(std::vector<const MachineBasicBlock*> &SB,
+ std::vector<std::vector<MachineBasicBlock*> > &prologues,
+ std::vector<std::vector<MachineBasicBlock*> > &epilogues,
+ std::vector<MachineBasicBlock*> &kernelBB,
+ std::map<Value*, MachineBasicBlock*> &newValLocation);
+
+ void writeEpilogues(std::vector<std::vector<MachineBasicBlock*> > &epilogues,
+ std::vector<const MachineBasicBlock*> &origSB,
+ std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
+ std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+ std::map<Value*, std::map<int, Value*> > &newValues,
+ std::map<Value*, MachineBasicBlock*> &newValLocation,
+ std::map<Value*, std::map<int, Value*> > &kernelPHIs);
+
+ void writeSideExits(std::vector<std::vector<MachineBasicBlock *> > &prologues,
+ std::vector<std::vector<BasicBlock*> > &llvm_prologues,
+ std::vector<std::vector<MachineBasicBlock *> > &epilogues,
+ std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
+ std::map<const MachineBasicBlock*, Value*> &sideExits,
+ std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > &instrsMovedDown,
+ std::vector<const MachineBasicBlock*> &SB,
+ std::vector<MachineBasicBlock*> &kernelMBBs,
+ std::map<MachineBasicBlock*, int> branchStage);
public:
ModuloSchedulingSBPass(TargetMachine &targ) : target(targ) {}
virtual bool runOnFunction(Function &F);
virtual const char* getPassName() const { return "ModuloScheduling-SuperBlock"; }
-
-
+
+
// getAnalysisUsage
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- /// HACK: We don't actually need scev, but we have
- /// to say we do so that the pass manager does not delete it
- /// before we run.
- AU.addRequired<LoopInfo>();
- AU.addRequired<ScalarEvolution>();
- AU.addRequired<DependenceAnalyzer>();
+ /// HACK: We don't actually need scev, but we have
+ /// to say we do so that the pass manager does not delete it
+ /// before we run.
+ AU.addRequired<LoopInfo>();
+ AU.addRequired<ScalarEvolution>();
+ AU.addRequired<DependenceAnalyzer>();
}
};
}
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