[llvm-commits] CVS: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp MachineFunctionInfo.cpp MachineFunctionInfo.h MappingInfo.cpp MappingInfo.h SparcV9BurgISel.cpp SparcV9FrameInfo.h SparcV9InstrForest.h SparcV9Internals.h SparcV9PrologEpilogInserter.cpp SparcV9RegClassInfo.cpp SparcV9RegClassInfo.h SparcV9RegInfo.cpp SparcV9RegInfo.h SparcV9SchedInfo.cpp SparcV9TargetMachine.cpp SparcV9TmpInstr.cpp
Jeff Cohen
jeffc at jolt-lang.org
Tue Jul 26 22:54:01 PDT 2005
Changes in directory llvm/lib/Target/SparcV9:
EmitBytecodeToAssembly.cpp updated: 1.16 -> 1.17
MachineFunctionInfo.cpp updated: 1.3 -> 1.4
MachineFunctionInfo.h updated: 1.10 -> 1.11
MappingInfo.cpp updated: 1.22 -> 1.23
MappingInfo.h updated: 1.11 -> 1.12
SparcV9BurgISel.cpp updated: 1.22 -> 1.23
SparcV9FrameInfo.h updated: 1.9 -> 1.10
SparcV9InstrForest.h updated: 1.3 -> 1.4
SparcV9Internals.h updated: 1.121 -> 1.122
SparcV9PrologEpilogInserter.cpp updated: 1.48 -> 1.49
SparcV9RegClassInfo.cpp updated: 1.41 -> 1.42
SparcV9RegClassInfo.h updated: 1.30 -> 1.31
SparcV9RegInfo.cpp updated: 1.141 -> 1.142
SparcV9RegInfo.h updated: 1.19 -> 1.20
SparcV9SchedInfo.cpp updated: 1.14 -> 1.15
SparcV9TargetMachine.cpp updated: 1.139 -> 1.140
SparcV9TmpInstr.cpp updated: 1.5 -> 1.6
---
Log message:
Eliminate tabs and trailing spaces.
---
Diffs of the changes: (+334 -334)
EmitBytecodeToAssembly.cpp | 4
MachineFunctionInfo.cpp | 10 -
MachineFunctionInfo.h | 14 +-
MappingInfo.cpp | 4
MappingInfo.h | 6
SparcV9BurgISel.cpp | 254 ++++++++++++++++++++--------------------
SparcV9FrameInfo.h | 2
SparcV9InstrForest.h | 88 ++++++-------
SparcV9Internals.h | 24 +--
SparcV9PrologEpilogInserter.cpp | 4
SparcV9RegClassInfo.cpp | 24 +--
SparcV9RegClassInfo.h | 2
SparcV9RegInfo.cpp | 62 ++++-----
SparcV9RegInfo.h | 6
SparcV9SchedInfo.cpp | 158 ++++++++++++------------
SparcV9TargetMachine.cpp | 4
SparcV9TmpInstr.cpp | 2
17 files changed, 334 insertions(+), 334 deletions(-)
Index: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
diff -u llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.16 llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.17
--- llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.16 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp Wed Jul 27 00:53:43 2005
@@ -62,7 +62,7 @@
};
static void writePrologue (std::ostream &Out, const std::string &comment,
- const std::string &symName) {
+ const std::string &symName) {
// Prologue:
// Output a comment describing the object.
Out << "!" << comment << "\n";
@@ -80,7 +80,7 @@
Out << ".end_" << symName << ":\n";
// Output size directive giving the size of the object:
Out << "\t.size " << symName << ", .end_" << symName << "-" << symName
- << "\n";
+ << "\n";
}
// SparcV9BytecodeWriter - Write bytecode out to a stream that is sparc'ified
Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp
diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.3 llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.4
--- llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.3 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp Wed Jul 27 00:53:43 2005
@@ -71,15 +71,15 @@
void SparcV9FunctionInfo::CalculateArgSize() {
maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(),
- MF.getFunction(),
+ MF.getFunction(),
maxOptionalNumArgs);
staticStackSize = maxOptionalArgsSize + 176;
}
int
SparcV9FunctionInfo::computeOffsetforLocalVar(const Value* val,
- unsigned &getPaddedSize,
- unsigned sizeToUse)
+ unsigned &getPaddedSize,
+ unsigned sizeToUse)
{
if (sizeToUse == 0) {
// All integer types smaller than ints promote to 4 byte integers.
@@ -92,7 +92,7 @@
bool growUp;
int firstOffset = MF.getTarget().getFrameInfo()->getFirstAutomaticVarOffset(MF,
- growUp);
+ growUp);
int offset = growUp? firstOffset + getAutomaticVarsSize()
: firstOffset - (getAutomaticVarsSize() + sizeToUse);
@@ -158,7 +158,7 @@
: firstOffset - (currentTmpValuesSize + size);
int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp,
- align);
+ align);
size += abs(aligned - offset); // include alignment padding in size
incrementTmpAreaSize(size); // update "current" size of tmp area
Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.h
diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.10 llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.11
--- llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.10 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/MachineFunctionInfo.h Wed Jul 27 00:53:43 2005
@@ -33,13 +33,13 @@
hash_set<const Constant*> constantsForConstPool;
hash_map<const Value*, int> offsets;
- unsigned staticStackSize;
- unsigned automaticVarsSize;
- unsigned regSpillsSize;
- unsigned maxOptionalArgsSize;
- unsigned maxOptionalNumArgs;
- unsigned currentTmpValuesSize;
- unsigned maxTmpValuesSize;
+ unsigned staticStackSize;
+ unsigned automaticVarsSize;
+ unsigned regSpillsSize;
+ unsigned maxOptionalArgsSize;
+ unsigned maxOptionalNumArgs;
+ unsigned currentTmpValuesSize;
+ unsigned maxTmpValuesSize;
bool compiledAsLeaf;
bool spillsAreaFrozen;
bool automaticVarsAreaFrozen;
Index: llvm/lib/Target/SparcV9/MappingInfo.cpp
diff -u llvm/lib/Target/SparcV9/MappingInfo.cpp:1.22 llvm/lib/Target/SparcV9/MappingInfo.cpp:1.23
--- llvm/lib/Target/SparcV9/MappingInfo.cpp:1.22 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/MappingInfo.cpp Wed Jul 27 00:53:43 2005
@@ -158,11 +158,11 @@
void MappingInfo::byteVector::dumpAssembly (std::ostream &Out) {
for (iterator i = begin (), e = end (); i != e; ++i)
- Out << ".byte " << (int)*i << "\n";
+ Out << ".byte " << (int)*i << "\n";
}
static void writePrologue (std::ostream &Out, const std::string &comment,
- const std::string &symName) {
+ const std::string &symName) {
// Prologue:
// Output a comment describing the object.
Out << "!" << comment << "\n";
Index: llvm/lib/Target/SparcV9/MappingInfo.h
diff -u llvm/lib/Target/SparcV9/MappingInfo.h:1.11 llvm/lib/Target/SparcV9/MappingInfo.h:1.12
--- llvm/lib/Target/SparcV9/MappingInfo.h:1.11 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/MappingInfo.h Wed Jul 27 00:53:43 2005
@@ -37,11 +37,11 @@
public:
void outByte (unsigned char b) { bytes.push_back (b); }
MappingInfo (std::string Comment, std::string SymbolPrefix,
- unsigned FunctionNumber) : comment(Comment),
- symbolPrefix(SymbolPrefix), functionNumber(FunctionNumber) {}
+ unsigned FunctionNumber) : comment(Comment),
+ symbolPrefix(SymbolPrefix), functionNumber(FunctionNumber) {}
void dumpAssembly (std::ostream &Out);
unsigned char *getBytes (unsigned &length) {
- length = bytes.size(); return &bytes[0];
+ length = bytes.size(); return &bytes[0];
}
};
Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.22 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.23
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.22 Wed Jun 22 16:04:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Wed Jul 27 00:53:43 2005
@@ -11,7 +11,7 @@
// construct a forest of BURG instruction trees (class InstrForest) and then
// uses the BURG-generated tree grammar (BURM) to find the optimal instruction
// sequences for the SparcV9.
-//
+//
//===----------------------------------------------------------------------===//
#include "MachineInstrAnnot.h"
@@ -157,8 +157,8 @@
RootSet treeRoots;
public:
- /*ctor*/ InstrForest (Function *F);
- /*dtor*/ ~InstrForest ();
+ /*ctor*/ InstrForest (Function *F);
+ /*dtor*/ ~InstrForest ();
/// getTreeNodeForInstr - Returns the tree node for an Instruction.
///
@@ -203,18 +203,18 @@
// Distinguish special cases of some instructions such as Ret and Br
//
if (opLabel == Instruction::Ret && cast<ReturnInst>(I)->getReturnValue()) {
- opLabel = RetValueOp; // ret(value) operation
+ opLabel = RetValueOp; // ret(value) operation
}
else if (opLabel ==Instruction::Br && !cast<BranchInst>(I)->isUnconditional())
{
- opLabel = BrCondOp; // br(cond) operation
+ opLabel = BrCondOp; // br(cond) operation
} else if (opLabel >= Instruction::SetEQ && opLabel <= Instruction::SetGT) {
- opLabel = SetCCOp; // common label for all SetCC ops
+ opLabel = SetCCOp; // common label for all SetCC ops
} else if (opLabel == Instruction::Alloca && I->getNumOperands() > 0) {
- opLabel = AllocaN; // Alloca(ptr, N) operation
+ opLabel = AllocaN; // Alloca(ptr, N) operation
} else if (opLabel == Instruction::GetElementPtr &&
cast<GetElementPtrInst>(I)->hasIndices()) {
- opLabel = opLabel + 100; // getElem with index vector
+ opLabel = opLabel + 100; // getElem with index vector
} else if (opLabel == Instruction::Xor &&
BinaryOperator::isNot(I)) {
opLabel = (I->getType() == Type::BoolTy)? NotOp // boolean Not operator
@@ -223,7 +223,7 @@
opLabel == Instruction::Xor) {
// Distinguish bitwise operators from logical operators!
if (I->getType() != Type::BoolTy)
- opLabel = opLabel + 100; // bitwise operator
+ opLabel = opLabel + 100; // bitwise operator
} else if (opLabel == Instruction::Cast) {
const Type *ITy = I->getType();
switch(ITy->getTypeID())
@@ -310,7 +310,7 @@
inline void InstrForest::noteTreeNodeForInstr(Instruction *instr,
InstructionNode *treeNode) {
(*this)[instr] = treeNode;
- treeRoots.push_back(treeNode); // mark node as root of a new tree
+ treeRoots.push_back(treeNode); // mark node as root of a new tree
}
inline void InstrForest::setLeftChild(InstrTreeNode *parent,
@@ -369,19 +369,19 @@
// that should be considered a data value.
// Check latter condition here just to simplify the next IF.
bool includeAddressOperand =
- (isa<BasicBlock>(operand) || isa<Function>(operand))
- && !instr->isTerminator();
+ (isa<BasicBlock>(operand) || isa<Function>(operand))
+ && !instr->isTerminator();
if (includeAddressOperand || isa<Instruction>(operand) ||
- isa<Constant>(operand) || isa<Argument>(operand)) {
+ isa<Constant>(operand) || isa<Argument>(operand)) {
// This operand is a data value.
// An instruction that computes the incoming value is added as a
// child of the current instruction if:
// the value has only a single use
// AND both instructions are in the same basic block.
// AND the current instruction is not a PHI (because the incoming
- // value is conceptually in a predecessor block,
- // even though it may be in the same static block)
+ // value is conceptually in a predecessor block,
+ // even though it may be in the same static block)
// (Note that if the value has only a single use (viz., `instr'),
// the def of the value can be safely moved just before instr
// and therefore it is safe to combine these two instructions.)
@@ -667,7 +667,7 @@
static inline void
CreateSETSWConst(int32_t C,
Instruction* dest, std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi, Value* val) {
+ MachineCodeForInstruction& mcfi, Value* val) {
//TmpInstruction for intermediate values
TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val);
@@ -693,7 +693,7 @@
CreateSETXConst(uint64_t C,
Instruction* tmpReg, Instruction* dest,
std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi, Value* val) {
+ MachineCodeForInstruction& mcfi, Value* val) {
assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
MachineInstr* MI;
@@ -746,7 +746,7 @@
static inline void
CreateSETXLabel(Value* val, Instruction* tmpReg,
Instruction* dest, std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) {
+ MachineCodeForInstruction& mcfi) {
assert(isa<Constant>(val) &&
"I only know about constant values and global addresses");
@@ -1396,8 +1396,8 @@
MachineOperand::MachineOperandType
ChooseRegOrImmed(Value* val,
MachineOpCode opCode, const TargetMachine& target,
- bool canUseImmed, unsigned int& getMachineRegNum,
- int64_t& getImmedValue) {
+ bool canUseImmed, unsigned int& getMachineRegNum,
+ int64_t& getImmedValue) {
getMachineRegNum = 0;
getImmedValue = 0;
@@ -2130,7 +2130,7 @@
// Cases worth optimizing are:
// (1) Add with 0 for float or double: use an FMOV of appropriate type,
- // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
+ // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
double dval = FPC->getValue();
if (dval == 0.0)
@@ -2166,7 +2166,7 @@
// Cases worth optimizing are:
// (1) Sub with 0 for float or double: use an FMOV of appropriate type,
- // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
+ // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
double dval = FPC->getValue();
if (dval == 0.0)
@@ -2324,31 +2324,31 @@
M = BuildMI(V9::ADDr,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
mvec.push_back(M);
} else if (isPowerOf2(C, pow)) {
- if(!needNeg) {
+ if(!needNeg) {
unsigned opSize = target.getTargetData().getTypeSize(resultType);
MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
destVal, mvec, mcfi);
- }
- else {
- //Create tmp instruction to hold intermeidate value, since we need
- //to negate the result
- tmpNeg = new TmpInstruction(mcfi, lval);
- unsigned opSize = target.getTargetData().getTypeSize(resultType);
- MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
- CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
- tmpNeg, mvec, mcfi);
- }
-
+ }
+ else {
+ //Create tmp instruction to hold intermeidate value, since we need
+ //to negate the result
+ tmpNeg = new TmpInstruction(mcfi, lval);
+ unsigned opSize = target.getTargetData().getTypeSize(resultType);
+ MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
+ CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
+ tmpNeg, mvec, mcfi);
+ }
+
}
if (mvec.size() > 0 && needNeg) {
- MachineInstr* M = 0;
- if(tmpNeg)
+ MachineInstr* M = 0;
+ if(tmpNeg)
// insert <reg = SUB 0, reg> after the instr to flip the sign
- M = CreateIntNegInstruction(target, tmpNeg, destVal);
- else
- M = CreateIntNegInstruction(target, destVal);
+ M = CreateIntNegInstruction(target, tmpNeg, destVal);
+ else
+ M = CreateIntNegInstruction(target, destVal);
mvec.push_back(M);
}
}
@@ -2495,13 +2495,13 @@
// sra N, 31, t1 // t1 = ~0, if N < 0, 0 else
// srl t1, 32-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
- // sra t3, k, result // result = N / 2^k
+ // sra t3, k, result // result = N / 2^k
//
// If N is 64 bits, use:
// srax N, k-1, t1 // t1 = sign bit in high k positions
// srlx t1, 64-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
- // sra t3, k, result // result = N / 2^k
+ // sra t3, k, result // result = N / 2^k
TmpInstruction *sraTmp, *srlTmp, *addTmp;
MachineCodeForInstruction& mcfi
= MachineCodeForInstruction::get(destVal);
@@ -2661,8 +2661,8 @@
if (((int)paddedSize) > 8 * SparcV9FrameInfo::SizeOfEachArgOnStack ||
!target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
CreateCodeForVariableSizeAlloca(target, result, tsize,
- ConstantSInt::get(Type::IntTy,numElements),
- getMvec);
+ ConstantSInt::get(Type::IntTy,numElements),
+ getMvec);
return;
}
@@ -2684,8 +2684,8 @@
/// offset is not a constant or if it cannot fit in the offset field. Use
/// [reg+offset] in all other cases. This assumes that all array refs are
/// "lowered" to one of these forms:
-/// %x = load (subarray*) ptr, constant ; single constant offset
-/// %x = load (subarray*) ptr, offsetVal ; single non-constant offset
+/// %x = load (subarray*) ptr, constant ; single constant offset
+/// %x = load (subarray*) ptr, offsetVal ; single non-constant offset
/// Generally, this should happen via strength reduction + LICM. Also, strength
/// reduction should take care of using the same register for the loop index
/// variable and an array index, when that is profitable.
@@ -2900,7 +2900,7 @@
///
extern bool ThisIsAChainRule(int eruleno) {
switch(eruleno) {
- case 111: // stmt: reg
+ case 111: // stmt: reg
case 123:
case 124:
case 125:
@@ -2936,7 +2936,7 @@
void GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode,
short* nts, TargetMachine &target,
std::vector<MachineInstr*>& mvec) {
- bool checkCast = false; // initialize here to use fall-through
+ bool checkCast = false; // initialize here to use fall-through
bool maskUnsignedResult = false;
int nextRule;
int forwardOperandNum = -1;
@@ -2967,11 +2967,11 @@
case 1: // stmt: Ret
case 2: // stmt: RetValue(reg)
{ // NOTE: Prepass of register allocation is responsible
- // for moving return value to appropriate register.
+ // for moving return value to appropriate register.
// Copy the return value to the required return register.
// Mark the return Value as an implicit ref of the RET instr..
// Mark the return-address register as a hidden virtual reg.
- // Finally put a NOP in the delay slot.
+ // Finally put a NOP in the delay slot.
ReturnInst *returnInstr=cast<ReturnInst>(subtreeRoot->getInstruction());
Value* retVal = returnInstr->getReturnValue();
MachineCodeForInstruction& mcfi =
@@ -3047,14 +3047,14 @@
break;
}
- case 3: // stmt: Store(reg,reg)
- case 4: // stmt: Store(reg,ptrreg)
+ case 3: // stmt: Store(reg,reg)
+ case 4: // stmt: Store(reg,ptrreg)
SetOperandsForMemInstr(ChooseStoreInstruction(
subtreeRoot->leftChild()->getValue()->getType()),
mvec, subtreeRoot, target);
break;
- case 5: // stmt: BrUncond
+ case 5: // stmt: BrUncond
{
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(0)));
@@ -3064,7 +3064,7 @@
break;
}
- case 206: // stmt: BrCond(setCCconst)
+ case 206: // stmt: BrCond(setCCconst)
{ // setCCconst => boolean was computed with `%b = setCC type reg1 const'
// If the constant is ZERO, we can use the branch-on-integer-register
// instructions and avoid the SUBcc instruction entirely.
@@ -3111,7 +3111,7 @@
// ELSE FALL THROUGH
}
- case 6: // stmt: BrCond(setCC)
+ case 6: // stmt: BrCond(setCC)
{ // bool => boolean was computed with SetCC.
// The branch to use depends on whether it is FP, signed, or unsigned.
// If it is an integer CC, we also need to find the unique
@@ -3139,7 +3139,7 @@
break;
}
- case 208: // stmt: BrCond(boolconst)
+ case 208: // stmt: BrCond(boolconst)
{
// boolconst => boolean is a constant; use BA to first or second label
Constant* constVal =
@@ -3155,7 +3155,7 @@
break;
}
- case 8: // stmt: BrCond(boolreg)
+ case 8: // stmt: BrCond(boolreg)
{ // boolreg => boolean is recorded in an integer register.
// Use branch-on-integer-register instruction.
//
@@ -3175,15 +3175,15 @@
break;
}
- case 9: // stmt: Switch(reg)
+ case 9: // stmt: Switch(reg)
assert(0 && "*** SWITCH instruction is not implemented yet.");
break;
- case 10: // reg: VRegList(reg, reg)
+ case 10: // reg: VRegList(reg, reg)
assert(0 && "VRegList should never be the topmost non-chain rule");
break;
- case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg
+ case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg
{ // First find the unary operand. It may be left or right, usually right.
Instruction* notI = subtreeRoot->getInstruction();
Value* notArg = BinaryOperator::getNotArgument(
@@ -3202,7 +3202,7 @@
break;
}
- case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0
+ case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0
{ // First find the unary operand. It may be left or right, usually right.
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(subtreeRoot->getInstruction()));
@@ -3212,18 +3212,18 @@
break;
}
- case 322: // reg: Not(tobool, reg):
+ case 322: // reg: Not(tobool, reg):
// Fold CAST-TO-BOOL with NOT by inverting the sense of cast-to-bool
foldCase = true;
// Just fall through!
- case 22: // reg: ToBoolTy(reg):
+ case 22: // reg: ToBoolTy(reg):
{
Instruction* castI = subtreeRoot->getInstruction();
Value* opVal = subtreeRoot->leftChild()->getValue();
- MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
- TmpInstruction* tempReg =
- new TmpInstruction(mcfi, opVal);
+ MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
+ TmpInstruction* tempReg =
+ new TmpInstruction(mcfi, opVal);
@@ -3243,14 +3243,14 @@
break;
}
- case 23: // reg: ToUByteTy(reg)
- case 24: // reg: ToSByteTy(reg)
- case 25: // reg: ToUShortTy(reg)
- case 26: // reg: ToShortTy(reg)
- case 27: // reg: ToUIntTy(reg)
- case 28: // reg: ToIntTy(reg)
- case 29: // reg: ToULongTy(reg)
- case 30: // reg: ToLongTy(reg)
+ case 23: // reg: ToUByteTy(reg)
+ case 24: // reg: ToSByteTy(reg)
+ case 25: // reg: ToUShortTy(reg)
+ case 26: // reg: ToShortTy(reg)
+ case 27: // reg: ToUIntTy(reg)
+ case 28: // reg: ToIntTy(reg)
+ case 29: // reg: ToULongTy(reg)
+ case 30: // reg: ToLongTy(reg)
{
//======================================================================
// Rules for integer conversions:
@@ -3356,9 +3356,9 @@
break;
}
- case 31: // reg: ToFloatTy(reg):
- case 32: // reg: ToDoubleTy(reg):
- case 232: // reg: ToDoubleTy(Constant):
+ case 31: // reg: ToFloatTy(reg):
+ case 32: // reg: ToDoubleTy(reg):
+ case 232: // reg: ToDoubleTy(Constant):
// If this instruction has a parent (a user) in the tree
// and the user is translated as an FsMULd instruction,
@@ -3415,12 +3415,12 @@
}
break;
- case 19: // reg: ToArrayTy(reg):
- case 20: // reg: ToPointerTy(reg):
+ case 19: // reg: ToArrayTy(reg):
+ case 20: // reg: ToPointerTy(reg):
forwardOperandNum = 0; // forward first operand to user
break;
- case 233: // reg: Add(reg, Constant)
+ case 233: // reg: Add(reg, Constant)
maskUnsignedResult = true;
M = CreateAddConstInstruction(subtreeRoot);
if (M != NULL) {
@@ -3429,12 +3429,12 @@
}
// ELSE FALL THROUGH
- case 33: // reg: Add(reg, reg)
+ case 33: // reg: Add(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec);
break;
- case 234: // reg: Sub(reg, Constant)
+ case 234: // reg: Sub(reg, Constant)
maskUnsignedResult = true;
M = CreateSubConstInstruction(subtreeRoot);
if (M != NULL) {
@@ -3443,18 +3443,18 @@
}
// ELSE FALL THROUGH
- case 34: // reg: Sub(reg, reg)
+ case 34: // reg: Sub(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseSubInstructionByType(
subtreeRoot->getInstruction()->getType()),
subtreeRoot, mvec);
break;
- case 135: // reg: Mul(todouble, todouble)
+ case 135: // reg: Mul(todouble, todouble)
checkCast = true;
// FALL THROUGH
- case 35: // reg: Mul(reg, reg)
+ case 35: // reg: Mul(reg, reg)
{
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
@@ -3468,11 +3468,11 @@
MachineCodeForInstruction::get(mulInstr),forceOp);
break;
}
- case 335: // reg: Mul(todouble, todoubleConst)
+ case 335: // reg: Mul(todouble, todoubleConst)
checkCast = true;
// FALL THROUGH
- case 235: // reg: Mul(reg, Constant)
+ case 235: // reg: Mul(reg, Constant)
{
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
@@ -3487,7 +3487,7 @@
forceOp);
break;
}
- case 236: // reg: Div(reg, Constant)
+ case 236: // reg: Div(reg, Constant)
maskUnsignedResult = true;
L = mvec.size();
CreateDivConstInstruction(target, subtreeRoot, mvec);
@@ -3495,7 +3495,7 @@
break;
// ELSE FALL THROUGH
- case 36: // reg: Div(reg, reg)
+ case 36: // reg: Div(reg, reg)
{
maskUnsignedResult = true;
@@ -3533,8 +3533,8 @@
break;
}
- case 37: // reg: Rem(reg, reg)
- case 237: // reg: Rem(reg, Constant)
+ case 37: // reg: Rem(reg, reg)
+ case 237: // reg: Rem(reg, Constant)
{
maskUnsignedResult = true;
@@ -3579,15 +3579,15 @@
break;
}
- case 38: // bool: And(bool, bool)
- case 138: // bool: And(bool, not)
- case 238: // bool: And(bool, boolconst)
- case 338: // reg : BAnd(reg, reg)
- case 538: // reg : BAnd(reg, Constant)
+ case 38: // bool: And(bool, bool)
+ case 138: // bool: And(bool, not)
+ case 238: // bool: And(bool, boolconst)
+ case 338: // reg : BAnd(reg, reg)
+ case 538: // reg : BAnd(reg, Constant)
Add3OperandInstr(V9::ANDr, subtreeRoot, mvec);
break;
- case 438: // bool: BAnd(bool, bnot)
+ case 438: // bool: BAnd(bool, bnot)
{ // Use the argument of NOT as the second argument!
// Mark the NOT node so that no code is generated for it.
// If the type is boolean, set 1 or 0 in the result register.
@@ -3609,15 +3609,15 @@
break;
}
- case 39: // bool: Or(bool, bool)
- case 139: // bool: Or(bool, not)
- case 239: // bool: Or(bool, boolconst)
- case 339: // reg : BOr(reg, reg)
- case 539: // reg : BOr(reg, Constant)
+ case 39: // bool: Or(bool, bool)
+ case 139: // bool: Or(bool, not)
+ case 239: // bool: Or(bool, boolconst)
+ case 339: // reg : BOr(reg, reg)
+ case 539: // reg : BOr(reg, Constant)
Add3OperandInstr(V9::ORr, subtreeRoot, mvec);
break;
- case 439: // bool: BOr(bool, bnot)
+ case 439: // bool: BOr(bool, bnot)
{ // Use the argument of NOT as the second argument!
// Mark the NOT node so that no code is generated for it.
// If the type is boolean, set 1 or 0 in the result register.
@@ -3640,15 +3640,15 @@
break;
}
- case 40: // bool: Xor(bool, bool)
- case 140: // bool: Xor(bool, not)
- case 240: // bool: Xor(bool, boolconst)
- case 340: // reg : BXor(reg, reg)
- case 540: // reg : BXor(reg, Constant)
+ case 40: // bool: Xor(bool, bool)
+ case 140: // bool: Xor(bool, not)
+ case 240: // bool: Xor(bool, boolconst)
+ case 340: // reg : BXor(reg, reg)
+ case 540: // reg : BXor(reg, Constant)
Add3OperandInstr(V9::XORr, subtreeRoot, mvec);
break;
- case 440: // bool: BXor(bool, bnot)
+ case 440: // bool: BXor(bool, bnot)
{ // Use the argument of NOT as the second argument!
// Mark the NOT node so that no code is generated for it.
// If the type is boolean, set 1 or 0 in the result register.
@@ -3669,7 +3669,7 @@
break;
}
- case 41: // setCCconst: SetCC(reg, Constant)
+ case 41: // setCCconst: SetCC(reg, Constant)
{ // Comparison is with a constant:
//
// If the bool result must be computed into a register (see below),
@@ -3720,7 +3720,7 @@
// ELSE FALL THROUGH
}
- case 42: // bool: SetCC(reg, reg):
+ case 42: // bool: SetCC(reg, reg):
{
// This generates a SUBCC instruction, putting the difference in a
// result reg. if needed, and/or setting a condition code if needed.
@@ -3816,22 +3816,22 @@
break;
}
- case 51: // reg: Load(reg)
- case 52: // reg: Load(ptrreg)
+ case 51: // reg: Load(reg)
+ case 52: // reg: Load(ptrreg)
SetOperandsForMemInstr(ChooseLoadInstruction(
subtreeRoot->getValue()->getType()),
mvec, subtreeRoot, target);
break;
- case 55: // reg: GetElemPtr(reg)
- case 56: // reg: GetElemPtrIdx(reg,reg)
+ case 55: // reg: GetElemPtr(reg)
+ case 56: // reg: GetElemPtrIdx(reg,reg)
// If the GetElemPtr was folded into the user (parent), it will be
// caught above. For other cases, we have to compute the address.
SetOperandsForMemInstr(V9::ADDr, mvec, subtreeRoot, target);
break;
- case 57: // reg: Alloca: Implement as 1 instruction:
- { // add %fp, offsetFromFP -> result
+ case 57: // reg: Alloca: Implement as 1 instruction:
+ { // add %fp, offsetFromFP -> result
AllocationInst* instr =
cast<AllocationInst>(subtreeRoot->getInstruction());
unsigned tsize =
@@ -3841,10 +3841,10 @@
break;
}
- case 58: // reg: Alloca(reg): Implement as 3 instructions:
- // mul num, typeSz -> tmp
- // sub %sp, tmp -> %sp
- { // add %sp, frameSizeBelowDynamicArea -> result
+ case 58: // reg: Alloca(reg): Implement as 3 instructions:
+ // mul num, typeSz -> tmp
+ // sub %sp, tmp -> %sp
+ { // add %sp, frameSizeBelowDynamicArea -> result
AllocationInst* instr =
cast<AllocationInst>(subtreeRoot->getInstruction());
const Type* eltType = instr->getAllocatedType();
@@ -3868,7 +3868,7 @@
break;
}
- case 61: // reg: Call
+ case 61: // reg: Call
{ // Generate a direct (CALL) or indirect (JMPL) call.
// Mark the return-address register, the indirection
// register (for indirect calls), the operands of the Call,
@@ -4191,7 +4191,7 @@
break;
}
- case 62: // reg: Shl(reg, reg)
+ case 62: // reg: Shl(reg, reg)
{
Value* argVal1 = subtreeRoot->leftChild()->getValue();
Value* argVal2 = subtreeRoot->rightChild()->getValue();
@@ -4209,7 +4209,7 @@
break;
}
- case 63: // reg: Shr(reg, reg)
+ case 63: // reg: Shr(reg, reg)
{
const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
assert((opType->isInteger() || isa<PointerType>(opType)) &&
@@ -4222,10 +4222,10 @@
break;
}
- case 64: // reg: Phi(reg,reg)
+ case 64: // reg: Phi(reg,reg)
break; // don't forward the value
- case 66: // reg: VAArg (reg): the va_arg instruction
+ case 66: // reg: VAArg (reg): the va_arg instruction
{ // Load argument from stack using current va_list pointer value.
// Use 64-bit load for all non-FP args, and LDDF or double for FP.
Instruction* vaArgI = subtreeRoot->getInstruction();
@@ -4255,8 +4255,8 @@
break;
}
- case 71: // reg: VReg
- case 72: // reg: Constant
+ case 71: // reg: VReg
+ case 72: // reg: Constant
break; // don't forward the value
default:
Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.9 llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.10
--- llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.9 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.h Wed Jul 27 00:53:43 2005
@@ -53,7 +53,7 @@
}
virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
- unsigned argNum) const {
+ unsigned argNum) const {
return FirstOutgoingArgOffsetFromSP + argNum * SizeOfEachArgOnStack;
}
Index: llvm/lib/Target/SparcV9/SparcV9InstrForest.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.3 llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.4
--- llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.3 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9InstrForest.h Wed Jul 27 00:53:43 2005
@@ -10,7 +10,7 @@
// A forest of BURG instruction trees (class InstrForest) which represents
// a function to the BURG-based instruction selector, and a bunch of constants
// and declarations used by the generated BURG code.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef SPARCV9INSTRFOREST_H
@@ -24,36 +24,36 @@
/// opcode returned by Instruction::getOpcode().
///
static const int
- InvalidOp = -1,
+ InvalidOp = -1,
VRegListOp = 97,
- VRegNodeOp = 98,
+ VRegNodeOp = 98,
ConstantNodeOp = 99,
- LabelNodeOp = 100,
- RetValueOp = 100 + Instruction::Ret, // 101
- BrCondOp = 100 + Instruction::Br, // 102
+ LabelNodeOp = 100,
+ RetValueOp = 100 + Instruction::Ret, // 101
+ BrCondOp = 100 + Instruction::Br, // 102
BAndOp = 100 + Instruction::And, // 111
BOrOp = 100 + Instruction::Or, // 112
BXorOp = 100 + Instruction::Xor, // 113
BNotOp = 200 + Instruction::Xor, // 213
NotOp = 300 + Instruction::Xor, // 313
- SetCCOp = 100 + Instruction::SetEQ, // 114
- AllocaN = 100 + Instruction::Alloca, // 122
- LoadIdx = 100 + Instruction::Load, // 123
- GetElemPtrIdx = 100 + Instruction::GetElementPtr, // 125
- ToBoolTy = 100 + Instruction::Cast; // 127
+ SetCCOp = 100 + Instruction::SetEQ, // 114
+ AllocaN = 100 + Instruction::Alloca, // 122
+ LoadIdx = 100 + Instruction::Load, // 123
+ GetElemPtrIdx = 100 + Instruction::GetElementPtr, // 125
+ ToBoolTy = 100 + Instruction::Cast; // 127
static const int
- ToUByteTy = ToBoolTy + 1,
- ToSByteTy = ToBoolTy + 2,
- ToUShortTy = ToBoolTy + 3,
- ToShortTy = ToBoolTy + 4,
- ToUIntTy = ToBoolTy + 5,
- ToIntTy = ToBoolTy + 6,
- ToULongTy = ToBoolTy + 7,
- ToLongTy = ToBoolTy + 8,
- ToFloatTy = ToBoolTy + 9,
- ToDoubleTy = ToBoolTy + 10,
- ToArrayTy = ToBoolTy + 11,
- ToPointerTy = ToBoolTy + 12;
+ ToUByteTy = ToBoolTy + 1,
+ ToSByteTy = ToBoolTy + 2,
+ ToUShortTy = ToBoolTy + 3,
+ ToShortTy = ToBoolTy + 4,
+ ToUIntTy = ToBoolTy + 5,
+ ToIntTy = ToBoolTy + 6,
+ ToULongTy = ToBoolTy + 7,
+ ToLongTy = ToBoolTy + 8,
+ ToFloatTy = ToBoolTy + 9,
+ ToDoubleTy = ToBoolTy + 10,
+ ToArrayTy = ToBoolTy + 11,
+ ToPointerTy = ToBoolTy + 12;
/// Data types needed by BURG
///
@@ -65,17 +65,17 @@
namespace llvm {
class InstrTreeNode;
};
-extern short* burm_nts[];
-extern StateLabel burm_label (InstrTreeNode* p);
-extern StateLabel burm_state (OpLabel op, StateLabel leftState,
- StateLabel rightState);
-extern StateLabel burm_rule (StateLabel state, int goalNT);
-extern InstrTreeNode** burm_kids (InstrTreeNode* p, int eruleno,
- InstrTreeNode* kids[]);
-extern void printcover (InstrTreeNode*, int, int);
-extern void printtree (InstrTreeNode*);
-extern int treecost (InstrTreeNode*, int, int);
-extern void printMatches (InstrTreeNode*);
+extern short* burm_nts[];
+extern StateLabel burm_label (InstrTreeNode* p);
+extern StateLabel burm_state (OpLabel op, StateLabel leftState,
+ StateLabel rightState);
+extern StateLabel burm_rule (StateLabel state, int goalNT);
+extern InstrTreeNode** burm_kids (InstrTreeNode* p, int eruleno,
+ InstrTreeNode* kids[]);
+extern void printcover (InstrTreeNode*, int, int);
+extern void printtree (InstrTreeNode*);
+extern int treecost (InstrTreeNode*, int, int);
+extern void printMatches (InstrTreeNode*);
namespace llvm {
@@ -87,10 +87,10 @@
void operator=(const InstrTreeNode &); // DO NOT IMPLEMENT
public:
enum InstrTreeNodeType { NTInstructionNode,
- NTVRegListNode,
- NTVRegNode,
- NTConstNode,
- NTLabelNode };
+ NTVRegListNode,
+ NTVRegNode,
+ NTConstNode,
+ NTLabelNode };
InstrTreeNode* LeftChild;
InstrTreeNode* RightChild;
InstrTreeNode* Parent;
@@ -99,7 +99,7 @@
protected:
InstrTreeNodeType treeNodeType;
- Value* val;
+ Value* val;
public:
InstrTreeNode(InstrTreeNodeType nodeType, Value* _val)
@@ -111,17 +111,17 @@
delete LeftChild;
delete RightChild;
}
- InstrTreeNodeType getNodeType () const { return treeNodeType; }
- Value* getValue () const { return val; }
- inline OpLabel getOpLabel () const { return opLabel; }
+ InstrTreeNodeType getNodeType () const { return treeNodeType; }
+ Value* getValue () const { return val; }
+ inline OpLabel getOpLabel () const { return opLabel; }
inline InstrTreeNode *leftChild () const { return LeftChild; }
inline InstrTreeNode *parent () const { return Parent; }
// If right child is a list node, recursively get its *left* child
inline InstrTreeNode* rightChild() const {
return (!RightChild ? 0 :
- (RightChild->getOpLabel() == VRegListOp
- ? RightChild->LeftChild : RightChild));
+ (RightChild->getOpLabel() == VRegListOp
+ ? RightChild->LeftChild : RightChild));
}
void dump(int dumpChildren, int indent) const;
protected:
Index: llvm/lib/Target/SparcV9/SparcV9Internals.h
diff -u llvm/lib/Target/SparcV9/SparcV9Internals.h:1.121 llvm/lib/Target/SparcV9/SparcV9Internals.h:1.122
--- llvm/lib/Target/SparcV9/SparcV9Internals.h:1.121 Sun Jun 12 18:52:58 2005
+++ llvm/lib/Target/SparcV9/SparcV9Internals.h Wed Jul 27 00:53:43 2005
@@ -31,18 +31,18 @@
class GetElementPtrInst;
enum SparcV9InstrSchedClass {
- SPARC_NONE, /* Instructions with no scheduling restrictions */
- SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
- SPARC_IEU0, /* Integer class IEU0 */
- SPARC_IEU1, /* Integer class IEU1 */
- SPARC_FPM, /* FP Multiply or Divide instructions */
- SPARC_FPA, /* All other FP instructions */
- SPARC_CTI, /* Control-transfer instructions */
- SPARC_LD, /* Load instructions */
- SPARC_ST, /* Store instructions */
- SPARC_SINGLE, /* Instructions that must issue by themselves */
+ SPARC_NONE, /* Instructions with no scheduling restrictions */
+ SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
+ SPARC_IEU0, /* Integer class IEU0 */
+ SPARC_IEU1, /* Integer class IEU1 */
+ SPARC_FPM, /* FP Multiply or Divide instructions */
+ SPARC_FPA, /* All other FP instructions */
+ SPARC_CTI, /* Control-transfer instructions */
+ SPARC_LD, /* Load instructions */
+ SPARC_ST, /* Store instructions */
+ SPARC_SINGLE, /* Instructions that must issue by themselves */
- SPARC_INV, /* This should stay at the end for the next value */
+ SPARC_INV, /* This should stay at the end for the next value */
SPARC_NUM_SCHED_CLASSES = SPARC_INV
};
@@ -65,7 +65,7 @@
// End-of-array marker
INVALID_OPCODE,
- NUM_REAL_OPCODES = PHI, // number of valid opcodes
+ NUM_REAL_OPCODES = PHI, // number of valid opcodes
NUM_TOTAL_OPCODES = INVALID_OPCODE
};
}
Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.48 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.49
--- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.48 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Wed Jul 27 00:53:43 2005
@@ -82,8 +82,8 @@
// Do this by creating a code sequence equivalent to:
// SETSW -(stackSize), %g1
int uregNum = TM.getRegInfo()->getUnifiedRegNum(
- TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
- SparcV9IntRegClass::g1);
+ TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
+ SparcV9IntRegClass::g1);
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
.addMReg(uregNum, MachineOperand::Def);
Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.41 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.42
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.41 Sun Jun 12 18:52:58 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Wed Jul 27 00:53:43 2005
@@ -49,13 +49,13 @@
unsigned SugCol = LR->getSuggestedColor();
if (!IsColorUsedArr[SugCol]) {
if (LR->isSuggestedColorUsable()) {
- // if the suggested color is volatile, we should use it only if
- // there are no call interferences. Otherwise, it will get spilled.
- if (DEBUG_RA)
- std::cerr << "\n -Coloring with sug color: " << SugCol;
+ // if the suggested color is volatile, we should use it only if
+ // there are no call interferences. Otherwise, it will get spilled.
+ if (DEBUG_RA)
+ std::cerr << "\n -Coloring with sug color: " << SugCol;
- LR->setColor(LR->getSuggestedColor());
- return;
+ LR->setColor(LR->getSuggestedColor());
+ return;
} else if(DEBUG_RA) {
std::cerr << "\n Couldn't alloc Sug col - LR volatile & calls interf";
}
@@ -195,8 +195,8 @@
// If the LR is a double try to allocate f32 - f63
// If the above fails or LR is single precision
// If the LR does not interfere with a call
-// start allocating from f0
-// Else start allocating from f6
+// start allocating from f0
+// Else start allocating from f6
// If a color is still not found because LR interferes with a call
// Search in f0 - f6. If found mark for spill across calls.
// If a color is still not fond, mark for spilling
@@ -298,8 +298,8 @@
// color could be found.
// Now try to allocate even a volatile color
ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
- SparcV9FloatRegClass::StartOfNonVolatileRegs,
- IsColorUsedArr);
+ SparcV9FloatRegClass::StartOfNonVolatileRegs,
+ IsColorUsedArr);
}
if (ColorFound >= 0) {
@@ -355,7 +355,7 @@
for (unsigned c = 0; c < NC; c+=2)
if (!IsColorUsedArr[c]) {
assert(!IsColorUsedArr[c+1] && "Incorrect used regs for FP double!");
- return c;
+ return c;
}
return -1;
}
@@ -381,7 +381,7 @@
if (!IsColorUsedArr[c]) {
assert(!IsColorUsedArr[c+1] &&
"Incorrect marking of used regs for SparcV9 FP double!");
- return c;
+ return c;
}
} else {
// find first unused color for a single
Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.30 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.31
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.30 Sun Jun 12 18:52:58 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h Wed Jul 27 00:53:43 2005
@@ -90,7 +90,7 @@
class SparcV9FloatRegClass : public TargetRegClassInfo {
int findFloatColor(const V9LiveRange *LR, unsigned Start,
- unsigned End,
+ unsigned End,
const std::vector<bool> &IsColorUsedArr) const;
public:
SparcV9FloatRegClass(unsigned ID)
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.141 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.142
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.141 Sun Jun 12 18:52:58 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Wed Jul 27 00:53:43 2005
@@ -211,7 +211,7 @@
getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
- return 0;
+ return 0;
}
}
@@ -313,7 +313,7 @@
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
- LiveRangeInfo& LRI) const {
+ LiveRangeInfo& LRI) const {
assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
@@ -366,7 +366,7 @@
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
- LiveRangeInfo& LRI) const
+ LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
bool isVarArgs = isVarArgsFunction(Meth->getType());
@@ -444,7 +444,7 @@
// if LR received the correct color, nothing to do
//
if( UniLRReg == UniArgReg )
- continue;
+ continue;
// We are here because the LR did not receive the suggested
// but LR received another register.
@@ -455,36 +455,36 @@
// the UniLRReg register
//
if( isArgInReg ) {
- if( regClassIDOfArgReg != RegClassID ) {
- // NOTE: This code has not been well-tested.
+ if( regClassIDOfArgReg != RegClassID ) {
+ // NOTE: This code has not been well-tested.
- // It is a variable argument call: the float reg must go in a %o reg.
- // We have to move an int reg to a float reg via memory.
+ // It is a variable argument call: the float reg must go in a %o reg.
+ // We have to move an int reg to a float reg via memory.
//
assert(isVarArgs &&
RegClassID == FloatRegClassID &&
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
+ int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
getSpilledRegSize(regType));
- cpReg2MemMI(InstrnsBefore,
+ cpReg2MemMI(InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
- cpMem2RegMI(InstrnsBefore,
+ cpMem2RegMI(InstrnsBefore,
getFramePointer(), TmpOff, UniLRReg, regType);
- }
- else {
- cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
- }
+ }
+ else {
+ cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
+ }
}
else {
- // Now the arg is coming on stack. Since the LR received a register,
- // we just have to load the arg on stack into that register
- //
+ // Now the arg is coming on stack. Since the LR received a register,
+ // we just have to load the arg on stack into that register
+ //
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
- int offsetFromFP =
+ int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
@@ -498,7 +498,7 @@
offsetFromFP += slotSize - argSize;
}
- cpMem2RegMI(InstrnsBefore,
+ cpMem2RegMI(InstrnsBefore,
getFramePointer(), offsetFromFP, UniLRReg, regType);
}
@@ -513,12 +513,12 @@
if( isArgInReg ) {
- if( regClassIDOfArgReg != RegClassID ) {
+ if( regClassIDOfArgReg != RegClassID ) {
assert(0 &&
"FP arguments to a varargs function should be explicitly "
"copied to/from int registers by instruction selection!");
- // It must be a float arg for a variable argument call, which
+ // It must be a float arg for a variable argument call, which
// must come in a %o reg. Move the int reg to the stack.
//
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
@@ -535,14 +535,14 @@
else {
- // Now the arg is coming on stack. Since the LR did NOT
- // received a register as well, it is allocated a stack position. We
- // can simply change the stack position of the LR. We can do this,
- // since this method is called before any other method that makes
- // uses of the stack pos of the LR (e.g., updateMachineInstr)
+ // Now the arg is coming on stack. Since the LR did NOT
+ // received a register as well, it is allocated a stack position. We
+ // can simply change the stack position of the LR. We can do this,
+ // since this method is called before any other method that makes
+ // uses of the stack pos of the LR (e.g., updateMachineInstr)
//
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
- int offsetFromFP =
+ int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
@@ -556,7 +556,7 @@
offsetFromFP += slotSize - argSize;
}
- LR->modifySpillOffFromFP( offsetFromFP );
+ LR->modifySpillOffFromFP( offsetFromFP );
}
}
@@ -572,7 +572,7 @@
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
- LiveRangeInfo& LRI) const {
+ LiveRangeInfo& LRI) const {
assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@@ -690,7 +690,7 @@
int RegType) const {
assert( ((int)SrcReg != getInvalidRegNum()) &&
((int)DestReg != getInvalidRegNum()) &&
- "Invalid Register");
+ "Invalid Register");
MachineInstr * MI = NULL;
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.19 llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.20
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.19 Sun Jun 12 18:52:58 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.h Wed Jul 27 00:53:43 2005
@@ -129,7 +129,7 @@
// To find the register class used for a specified Type
//
unsigned getRegClassIDOfType (const Type *type,
- bool isCCReg = false) const;
+ bool isCCReg = false) const;
// To find the register class to which a specified register belongs
//
@@ -165,7 +165,7 @@
LiveRangeInfo& LRI) const;
void suggestReg4RetValue(MachineInstr *RetI,
- LiveRangeInfo& LRI) const;
+ LiveRangeInfo& LRI) const;
void colorMethodArgs(const Function *Func,
LiveRangeInfo &LRI,
@@ -259,7 +259,7 @@
// as required. See SparcV9RegInfo.cpp for the implementation.
//
void suggestReg4RetAddr(MachineInstr *RetMI,
- LiveRangeInfo &LRI) const;
+ LiveRangeInfo &LRI) const;
void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
Index: llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.14 llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.15
--- llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.14 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp Wed Jul 27 00:53:43 2005
@@ -71,7 +71,7 @@
-- Shift instructions cannot be grouped with other IEU0-specific instructions.
-- CC setting instructions cannot be grouped with other IEU1-specific instrs.
-- Several instructions must be issued in a single-instruction group:
- MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
+ MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
-- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
--
--
@@ -357,7 +357,7 @@
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
- { CTIIssueSlots.rid, 0, 1 },
+ { CTIIssueSlots.rid, 0, 1 },
/*Cycle E */ { IAlu0.rid, 1, 1 },
/*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
/*Cycle C */
@@ -423,79 +423,79 @@
// opCode, isSingleIssue, breaksGroup, numBubbles
- // Special cases for single-issue only
- // Other single issue cases are below.
-//{ V9::LDDA, true, true, 0 },
-//{ V9::STDA, true, true, 0 },
-//{ V9::LDDF, true, true, 0 },
-//{ V9::LDDFA, true, true, 0 },
- { V9::ADDCr, true, true, 0 },
- { V9::ADDCi, true, true, 0 },
- { V9::ADDCccr, true, true, 0 },
- { V9::ADDCcci, true, true, 0 },
- { V9::SUBCr, true, true, 0 },
- { V9::SUBCi, true, true, 0 },
- { V9::SUBCccr, true, true, 0 },
- { V9::SUBCcci, true, true, 0 },
-//{ V9::LDSTUB, true, true, 0 },
-//{ V9::SWAP, true, true, 0 },
-//{ V9::SWAPA, true, true, 0 },
-//{ V9::CAS, true, true, 0 },
-//{ V9::CASA, true, true, 0 },
-//{ V9::CASX, true, true, 0 },
-//{ V9::CASXA, true, true, 0 },
-//{ V9::LDFSR, true, true, 0 },
-//{ V9::LDFSRA, true, true, 0 },
-//{ V9::LDXFSR, true, true, 0 },
-//{ V9::LDXFSRA, true, true, 0 },
-//{ V9::STFSR, true, true, 0 },
-//{ V9::STFSRA, true, true, 0 },
-//{ V9::STXFSR, true, true, 0 },
-//{ V9::STXFSRA, true, true, 0 },
-//{ V9::SAVED, true, true, 0 },
-//{ V9::RESTORED, true, true, 0 },
-//{ V9::FLUSH, true, true, 9 },
-//{ V9::FLUSHW, true, true, 9 },
-//{ V9::ALIGNADDR, true, true, 0 },
-//{ V9::DONE, true, true, 0 },
-//{ V9::RETRY, true, true, 0 },
-//{ V9::TCC, true, true, 0 },
-//{ V9::SHUTDOWN, true, true, 0 },
-
- // Special cases for breaking group *before*
- // CURRENTLY NOT SUPPORTED!
- { V9::CALL, false, false, 0 },
- { V9::JMPLCALLr, false, false, 0 },
- { V9::JMPLCALLi, false, false, 0 },
- { V9::JMPLRETr, false, false, 0 },
- { V9::JMPLRETi, false, false, 0 },
-
- // Special cases for breaking the group *after*
- { V9::MULXr, true, true, (4+34)/2 },
- { V9::MULXi, true, true, (4+34)/2 },
- { V9::FDIVS, false, true, 0 },
- { V9::FDIVD, false, true, 0 },
- { V9::FDIVQ, false, true, 0 },
- { V9::FSQRTS, false, true, 0 },
- { V9::FSQRTD, false, true, 0 },
- { V9::FSQRTQ, false, true, 0 },
+ // Special cases for single-issue only
+ // Other single issue cases are below.
+//{ V9::LDDA, true, true, 0 },
+//{ V9::STDA, true, true, 0 },
+//{ V9::LDDF, true, true, 0 },
+//{ V9::LDDFA, true, true, 0 },
+ { V9::ADDCr, true, true, 0 },
+ { V9::ADDCi, true, true, 0 },
+ { V9::ADDCccr, true, true, 0 },
+ { V9::ADDCcci, true, true, 0 },
+ { V9::SUBCr, true, true, 0 },
+ { V9::SUBCi, true, true, 0 },
+ { V9::SUBCccr, true, true, 0 },
+ { V9::SUBCcci, true, true, 0 },
+//{ V9::LDSTUB, true, true, 0 },
+//{ V9::SWAP, true, true, 0 },
+//{ V9::SWAPA, true, true, 0 },
+//{ V9::CAS, true, true, 0 },
+//{ V9::CASA, true, true, 0 },
+//{ V9::CASX, true, true, 0 },
+//{ V9::CASXA, true, true, 0 },
+//{ V9::LDFSR, true, true, 0 },
+//{ V9::LDFSRA, true, true, 0 },
+//{ V9::LDXFSR, true, true, 0 },
+//{ V9::LDXFSRA, true, true, 0 },
+//{ V9::STFSR, true, true, 0 },
+//{ V9::STFSRA, true, true, 0 },
+//{ V9::STXFSR, true, true, 0 },
+//{ V9::STXFSRA, true, true, 0 },
+//{ V9::SAVED, true, true, 0 },
+//{ V9::RESTORED, true, true, 0 },
+//{ V9::FLUSH, true, true, 9 },
+//{ V9::FLUSHW, true, true, 9 },
+//{ V9::ALIGNADDR, true, true, 0 },
+//{ V9::DONE, true, true, 0 },
+//{ V9::RETRY, true, true, 0 },
+//{ V9::TCC, true, true, 0 },
+//{ V9::SHUTDOWN, true, true, 0 },
+
+ // Special cases for breaking group *before*
+ // CURRENTLY NOT SUPPORTED!
+ { V9::CALL, false, false, 0 },
+ { V9::JMPLCALLr, false, false, 0 },
+ { V9::JMPLCALLi, false, false, 0 },
+ { V9::JMPLRETr, false, false, 0 },
+ { V9::JMPLRETi, false, false, 0 },
+
+ // Special cases for breaking the group *after*
+ { V9::MULXr, true, true, (4+34)/2 },
+ { V9::MULXi, true, true, (4+34)/2 },
+ { V9::FDIVS, false, true, 0 },
+ { V9::FDIVD, false, true, 0 },
+ { V9::FDIVQ, false, true, 0 },
+ { V9::FSQRTS, false, true, 0 },
+ { V9::FSQRTD, false, true, 0 },
+ { V9::FSQRTQ, false, true, 0 },
//{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 },
- // Instructions that introduce bubbles
-//{ V9::MULScc, true, true, 2 },
-//{ V9::SMULcc, true, true, (4+18)/2 },
-//{ V9::UMULcc, true, true, (4+19)/2 },
- { V9::SDIVXr, true, true, 68 },
- { V9::SDIVXi, true, true, 68 },
- { V9::UDIVXr, true, true, 68 },
- { V9::UDIVXi, true, true, 68 },
-//{ V9::SDIVcc, true, true, 36 },
-//{ V9::UDIVcc, true, true, 37 },
- { V9::WRCCRr, true, true, 4 },
- { V9::WRCCRi, true, true, 4 },
-//{ V9::WRPR, true, true, 4 },
-//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
-//{ V9::RDPR, true, true, 0 },
+ // Instructions that introduce bubbles
+//{ V9::MULScc, true, true, 2 },
+//{ V9::SMULcc, true, true, (4+18)/2 },
+//{ V9::UMULcc, true, true, (4+19)/2 },
+ { V9::SDIVXr, true, true, 68 },
+ { V9::SDIVXi, true, true, 68 },
+ { V9::UDIVXr, true, true, 68 },
+ { V9::UDIVXi, true, true, 68 },
+//{ V9::SDIVcc, true, true, 36 },
+//{ V9::UDIVcc, true, true, 37 },
+ { V9::WRCCRr, true, true, 4 },
+ { V9::WRCCRi, true, true, 4 },
+//{ V9::WRPR, true, true, 4 },
+//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
+//{ V9::RDPR, true, true, 0 },
};
@@ -738,14 +738,14 @@
SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
: TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
- SparcV9RUsageDesc,
- SparcV9InstrUsageDeltas,
- SparcV9InstrIssueDeltas,
- sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
- sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
+ SparcV9RUsageDesc,
+ SparcV9InstrUsageDeltas,
+ SparcV9InstrIssueDeltas,
+ sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
+ sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
{
maxNumIssueTotal = 4;
- longestIssueConflict = 0; // computed from issuesGaps[]
+ longestIssueConflict = 0; // computed from issuesGaps[]
// must be called after above parameters are initialized.
initializeResources();
Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.139 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.140
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.139 Fri Jun 24 21:48:37 2005
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp Wed Jul 27 00:53:43 2005
@@ -64,10 +64,10 @@
cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
cl::opt<bool> EnableModSched("enable-modsched",
- cl::desc("Enable modulo scheduling pass"), cl::Hidden);
+ cl::desc("Enable modulo scheduling pass"), cl::Hidden);
cl::opt<bool> EnableSBModSched("enable-modschedSB",
- cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden);
+ cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden);
// Register the target.
RegisterTarget<SparcV9TargetMachine> X("sparcv9", " SPARC V9");
Index: llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.5 llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.6
--- llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.5 Thu Apr 21 18:25:42 2005
+++ llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp Wed Jul 27 00:53:43 2005
@@ -9,7 +9,7 @@
//
// Methods of class for temporary intermediate values used within the current
// SparcV9 backend.
-//
+//
//===----------------------------------------------------------------------===//
#include "SparcV9TmpInstr.h"
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