[llvm-commits] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetFrameInfo.h TargetInstrInfo.h TargetSchedInfo.h
Misha Brukman
brukman at cs.uiuc.edu
Thu Apr 21 20:46:36 PDT 2005
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.56 -> 1.57
TargetFrameInfo.h updated: 1.18 -> 1.19
TargetInstrInfo.h updated: 1.76 -> 1.77
TargetSchedInfo.h updated: 1.34 -> 1.35
---
Log message:
Convert tabs to spaces
---
Diffs of the changes: (+76 -79)
MRegisterInfo.h | 6 +--
TargetFrameInfo.h | 25 ++++++--------
TargetInstrInfo.h | 30 ++++++++---------
TargetSchedInfo.h | 94 +++++++++++++++++++++++++++---------------------------
4 files changed, 76 insertions(+), 79 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.56 llvm/include/llvm/Target/MRegisterInfo.h:1.57
--- llvm/include/llvm/Target/MRegisterInfo.h:1.56 Thu Apr 21 15:53:44 2005
+++ llvm/include/llvm/Target/MRegisterInfo.h Thu Apr 21 22:46:24 2005
@@ -123,7 +123,7 @@
protected:
MRegisterInfo(const MRegisterDesc *D, unsigned NR,
regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
- int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
+ int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
virtual ~MRegisterInfo();
public:
@@ -285,8 +285,8 @@
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
- "eliminateCallFramePseudoInstr must be implemented if using"
- " call frame setup/destroy pseudo instructions!");
+ "eliminateCallFramePseudoInstr must be implemented if using"
+ " call frame setup/destroy pseudo instructions!");
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
}
Index: llvm/include/llvm/Target/TargetFrameInfo.h
diff -u llvm/include/llvm/Target/TargetFrameInfo.h:1.18 llvm/include/llvm/Target/TargetFrameInfo.h:1.19
--- llvm/include/llvm/Target/TargetFrameInfo.h:1.18 Thu Apr 21 15:53:44 2005
+++ llvm/include/llvm/Target/TargetFrameInfo.h Thu Apr 21 22:46:24 2005
@@ -81,26 +81,23 @@
// This method adjusts a stack offset to meet alignment rules of target.
virtual int adjustAlignment(int unalignedOffset, bool growUp,
- unsigned align) const;
+ unsigned align) const;
// These methods compute offsets using the frame contents for a particular
// function. The frame contents are obtained from the MachineFunction object
// for the given function. The rest must be implemented by the
// machine-specific subclass.
//
- virtual int getIncomingArgOffset (MachineFunction& mcInfo,
- unsigned argNum) const;
- virtual int getOutgoingArgOffset (MachineFunction& mcInfo,
- unsigned argNum) const;
-
- virtual int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
- bool& growUp) const;
- virtual int getRegSpillAreaOffset (MachineFunction& mcInfo,
- bool& growUp) const;
- virtual int getTmpAreaOffset (MachineFunction& mcInfo,
- bool& growUp) const;
- virtual int getDynamicAreaOffset (MachineFunction& mcInfo,
- bool& growUp) const;
+ virtual int getIncomingArgOffset(MachineFunction& mcInfo,
+ unsigned argNum) const;
+ virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
+ unsigned argNum) const;
+ virtual int getFirstAutomaticVarOffset(MachineFunction& mcInfo,
+ bool& growUp) const;
+ virtual int getRegSpillAreaOffset(MachineFunction& mcInfo,
+ bool& growUp) const;
+ virtual int getTmpAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
+ virtual int getDynamicAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
};
} // End llvm namespace
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.76 llvm/include/llvm/Target/TargetInstrInfo.h:1.77
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.76 Thu Apr 21 15:53:44 2005
+++ llvm/include/llvm/Target/TargetInstrInfo.h Thu Apr 21 22:46:24 2005
@@ -39,22 +39,22 @@
//---------------------------------------------------------------------------
// struct TargetInstrDescriptor:
-// Predefined information about each machine instruction.
-// Designed to initialized statically.
+// Predefined information about each machine instruction.
+// Designed to initialized statically.
//
-const unsigned M_NOP_FLAG = 1 << 0;
-const unsigned M_BRANCH_FLAG = 1 << 1;
-const unsigned M_CALL_FLAG = 1 << 2;
-const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_BARRIER_FLAG = 1 << 4;
-const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
-const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOAD_FLAG = 1 << 7;
-const unsigned M_STORE_FLAG = 1 << 8;
+const unsigned M_NOP_FLAG = 1 << 0;
+const unsigned M_BRANCH_FLAG = 1 << 1;
+const unsigned M_CALL_FLAG = 1 << 2;
+const unsigned M_RET_FLAG = 1 << 3;
+const unsigned M_BARRIER_FLAG = 1 << 4;
+const unsigned M_DELAY_SLOT_FLAG = 1 << 5;
+const unsigned M_CC_FLAG = 1 << 6;
+const unsigned M_LOAD_FLAG = 1 << 7;
+const unsigned M_STORE_FLAG = 1 << 8;
// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones.
-const unsigned M_2_ADDR_FLAG = 1 << 9;
+const unsigned M_2_ADDR_FLAG = 1 << 9;
// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be
// changed into a 3-address instruction if the first two operands cannot be
@@ -78,7 +78,7 @@
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
+ bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned numDelaySlots; // Number of delay slots after instruction
unsigned latency; // Latency in machine cycles
@@ -275,7 +275,7 @@
// of this machine instruction
//
virtual bool constantFitsInImmedField(MachineOpCode Opcode,
- int64_t intValue) const;
+ int64_t intValue) const;
// Return the largest positive constant that can be held in the IMMED field
// of this machine instruction.
@@ -284,7 +284,7 @@
// Return 0 if the instruction has no IMMED field.
//
virtual uint64_t maxImmedConstant(MachineOpCode Opcode,
- bool &isSignExtended) const {
+ bool &isSignExtended) const {
isSignExtended = get(Opcode).immedIsSignExtended;
return get(Opcode).maxImmedConst;
}
Index: llvm/include/llvm/Target/TargetSchedInfo.h
diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.34 llvm/include/llvm/Target/TargetSchedInfo.h:1.35
--- llvm/include/llvm/Target/TargetSchedInfo.h:1.34 Thu Apr 21 15:53:44 2005
+++ llvm/include/llvm/Target/TargetSchedInfo.h Thu Apr 21 22:46:24 2005
@@ -72,13 +72,13 @@
struct InstrClassRUsage {
InstrSchedClass schedClass;
- int totCycles;
+ int totCycles;
// Issue restrictions common to instructions in this class
unsigned maxNumIssue;
- bool isSingleIssue;
- bool breaksGroup;
- CycleCount_t numBubbles;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
// Feasible slots to use for instructions in this class.
// The size of vector S[] is `numSlots'.
@@ -91,41 +91,41 @@
struct {
resourceId_t resourceId;
unsigned startCycle;
- int numCycles;
+ int numCycles;
} V[MAX_NUM_CYCLES];
};
struct InstrRUsageDelta {
MachineOpCode opCode;
- resourceId_t resourceId;
+ resourceId_t resourceId;
unsigned startCycle;
- int numCycles;
+ int numCycles;
};
// Specify instruction issue restrictions for individual instructions
// that differ from the common rules for the class.
//
struct InstrIssueDelta {
- MachineOpCode opCode;
- bool isSingleIssue;
- bool breaksGroup;
- CycleCount_t numBubbles;
+ MachineOpCode opCode;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
};
struct InstrRUsage {
- bool sameAsClass;
+ bool sameAsClass;
// Issue restrictions for this instruction
- bool isSingleIssue;
- bool breaksGroup;
- CycleCount_t numBubbles;
+ bool isSingleIssue;
+ bool breaksGroup;
+ CycleCount_t numBubbles;
// Feasible slots to use for this instruction.
std::vector<bool> feasibleSlots;
// Resource usages for this instruction, with one resource vector per cycle.
- CycleCount_t numCycles;
+ CycleCount_t numCycles;
std::vector<std::vector<resourceId_t> > resourcesByCycle;
private:
@@ -139,12 +139,12 @@
numBubbles = delta.numBubbles;
}
- void addUsageDelta (const InstrRUsageDelta& delta);
- void setMaxSlots (int maxNumSlots) {
+ void addUsageDelta(const InstrRUsageDelta& delta);
+ void setMaxSlots(int maxNumSlots) {
feasibleSlots.resize(maxNumSlots);
}
- friend class TargetSchedInfo; // give access to these functions
+ friend class TargetSchedInfo; // give access to these functions
};
@@ -157,7 +157,7 @@
const TargetMachine& target;
unsigned maxNumIssueTotal;
- int longestIssueConflict;
+ int longestIssueConflict;
protected:
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
@@ -173,20 +173,20 @@
TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT
void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT
public:
- /*ctor*/ TargetSchedInfo (const TargetMachine& tgt,
- int _numSchedClasses,
- const InstrClassRUsage* _classRUsages,
- const InstrRUsageDelta* _usageDeltas,
- const InstrIssueDelta* _issueDeltas,
- unsigned _numUsageDeltas,
- unsigned _numIssueDeltas);
- /*dtor*/ virtual ~TargetSchedInfo() {}
+ TargetSchedInfo(const TargetMachine& tgt,
+ int _numSchedClasses,
+ const InstrClassRUsage* _classRUsages,
+ const InstrRUsageDelta* _usageDeltas,
+ const InstrIssueDelta* _issueDeltas,
+ unsigned _numUsageDeltas,
+ unsigned _numIssueDeltas);
+ virtual ~TargetSchedInfo() {}
inline const TargetInstrInfo& getInstrInfo() const {
return *mii;
}
- inline int getNumSchedClasses() const {
+ inline int getNumSchedClasses() const {
return numSchedClasses;
}
@@ -199,42 +199,42 @@
return classRUsages[sc].maxNumIssue;
}
- inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
+ inline InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return getInstrInfo().getSchedClass(opCode);
}
- inline bool instrCanUseSlot (MachineOpCode opCode,
- unsigned s) const {
+ inline bool instrCanUseSlot(MachineOpCode opCode,
+ unsigned s) const {
assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
return getInstrRUsage(opCode).feasibleSlots[s];
}
- inline int getLongestIssueConflict () const {
+ inline int getLongestIssueConflict() const {
return longestIssueConflict;
}
- inline int getMinIssueGap (MachineOpCode fromOp,
- MachineOpCode toOp) const {
+ inline int getMinIssueGap(MachineOpCode fromOp,
+ MachineOpCode toOp) const {
assert(fromOp < (int) issueGaps.size());
const std::vector<int>& toGaps = issueGaps[fromOp];
return (toOp < (int) toGaps.size())? toGaps[toOp] : 0;
}
inline const std::vector<MachineOpCode>&
- getConflictList(MachineOpCode opCode) const {
+ getConflictList(MachineOpCode opCode) const {
assert(opCode < (int) conflictLists.size());
return conflictLists[opCode];
}
- inline bool isSingleIssue (MachineOpCode opCode) const {
+ inline bool isSingleIssue(MachineOpCode opCode) const {
return getInstrRUsage(opCode).isSingleIssue;
}
- inline bool breaksIssueGroup (MachineOpCode opCode) const {
+ inline bool breaksIssueGroup(MachineOpCode opCode) const {
return getInstrRUsage(opCode).breaksGroup;
}
- inline unsigned numBubblesAfter (MachineOpCode opCode) const {
+ inline unsigned numBubblesAfter(MachineOpCode opCode) const {
return getInstrRUsage(opCode).numBubbles;
}
@@ -248,7 +248,7 @@
protected:
- virtual void initializeResources ();
+ virtual void initializeResources();
private:
void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
@@ -265,18 +265,18 @@
std::vector<std::pair<int,int> > resourceNumVector;
protected:
- unsigned numSchedClasses;
+ unsigned numSchedClasses;
const TargetInstrInfo* mii;
- const InstrClassRUsage* classRUsages; // raw array by sclass
- const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
- const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
- unsigned numUsageDeltas;
- unsigned numIssueDeltas;
+ const InstrClassRUsage* classRUsages; // raw array by sclass
+ const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
+ const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
+ unsigned numUsageDeltas;
+ unsigned numIssueDeltas;
std::vector<InstrRUsage> instrRUsages; // indexed by opcode
std::vector<std::vector<int> > issueGaps; // indexed by [opcode1][opcode2]
std::vector<std::vector<MachineOpCode> >
- conflictLists; // indexed by [opcode]
+ conflictLists; // indexed by [opcode]
friend class ModuloSchedulingPass;
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