[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.94 -> 1.95
---
Log message:

added all flavors of zap for anding

---
Diffs of the changes:  (+20 -0)

 AlphaISelPattern.cpp |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.94 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.95
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.94	Tue Apr 12 21:43:40 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Apr 12 22:47:03 2005
@@ -1692,6 +1692,26 @@
       }
     //Fall through
   case ISD::AND:
+    //handle zap
+    if (opcode == ISD::AND && N.getOperand(1).getOpcode() == ISD::Constant)
+    {
+      uint64_t k = cast<ConstantSDNode>(N.getOperand(1))->getValue();
+      unsigned int build = 0;
+      for(int i = 0; i < 8; ++i)
+      {
+        if (k & 0xFF == 0xFF)
+          build |= 1 << i;
+        else if (k & 0xFF != 0)
+        { build = 0; break; }
+        k >>= 8;
+      }
+      if (build)
+      {
+        Tmp1 = SelectExpr(N.getOperand(0));
+        BuildMI(BB, Alpha::ZAPNOTi, 2, Result).addReg(Tmp1).addImm(build);
+        return Result;
+      }
+    }
   case ISD::OR:
     //Check operand(0) == Not
     if (N.getOperand(0).getOpcode() == ISD::XOR &&