[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.93 -> 1.94
---
Log message:

Remove support for ZERO_EXTEND_INREG.  This pessimizes code, genering stuff
like this:

        ldah $1,1($31)
        lda $1,-1($1)
        and $0,$1,$24

instead of this:

        zap $0,252,$24

To get this back, the selector should recognize the ISD::AND case where this
happens and emit the appropriate ZAP instruction.



---
Diffs of the changes:  (+0 -21)

 AlphaISelPattern.cpp |   21 ---------------------
 1 files changed, 21 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.93 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.94
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.93	Tue Apr 12 12:47:57 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Tue Apr 12 21:43:40 2005
@@ -1562,27 +1562,6 @@
       }
       return Result;
     }
-  case ISD::ZERO_EXTEND_INREG:
-    {
-      Tmp1 = SelectExpr(N.getOperand(0));
-      MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
-      //std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
-      switch(MVN->getExtraValueType())
-      {
-      default:
-        Node->dump();
-        assert(0 && "Zero Extend InReg not there yet");
-        break;
-      case MVT::i32: Tmp2 = 0xf0; break;
-      case MVT::i16: Tmp2 = 0xfc; break;
-      case MVT::i8: Tmp2 = 0xfe; break;
-      case MVT::i1: //handle this one special
-        BuildMI(BB, Alpha::ANDi, 2, Result).addReg(Tmp1).addImm(1);
-        return Result;
-      }
-      BuildMI(BB, Alpha::ZAPi, 2, Result).addReg(Tmp1).addImm(Tmp2);
-      return Result;
-    }
     
   case ISD::SETCC:
     {