[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Chris Lattner
lattner at cs.uiuc.edu
Mon Apr 11 13:30:16 PDT 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.82 -> 1.83
---
Log message:
Teach the dag mechanism that this:
long long test2(unsigned A, unsigned B) {
return ((unsigned long long)A << 32) + B;
}
is equivalent to this:
long long test1(unsigned A, unsigned B) {
return ((unsigned long long)A << 32) | B;
}
Now they are both codegen'd to this on ppc:
_test2:
blr
or this on x86:
test2:
movl 4(%esp), %edx
movl 8(%esp), %eax
ret
---
Diffs of the changes: (+21 -2)
LegalizeDAG.cpp | 23 +++++++++++++++++++++--
1 files changed, 21 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.82 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.83
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.82 Mon Apr 11 15:08:52 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr 11 15:29:59 2005
@@ -1443,8 +1443,27 @@
ExpandOp(LHS, LHSL, LHSH);
ExpandOp(RHS, RHSL, RHSH);
- // Convert this add to the appropriate ADDC pair. The low part has no carry
- // in.
+ // FIXME: this should be moved to the dag combiner someday.
+ if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS)
+ if (LHSL.getValueType() == MVT::i32) {
+ SDOperand LowEl;
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
+ if (C->getValue() == 0)
+ LowEl = RHSL;
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
+ if (C->getValue() == 0)
+ LowEl = LHSL;
+ if (LowEl.Val) {
+ // Turn this into an add/sub of the high part only.
+ SDOperand HiEl =
+ DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
+ LowEl.getValueType(), LHSH, RHSH);
+ Lo = LowEl;
+ Hi = HiEl;
+ return;
+ }
+ }
+
std::vector<SDOperand> Ops;
Ops.push_back(LHSL);
Ops.push_back(LHSH);
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