[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp
Chris Lattner
lattner at cs.uiuc.edu
Tue Apr 5 21:21:21 PDT 2005
Changes in directory llvm/lib/Target/X86:
X86ISelPattern.cpp updated: 1.99 -> 1.100
---
Log message:
Add (untested) support for MULHS and MULHU.
---
Diffs of the changes: (+51 -0)
X86ISelPattern.cpp | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+)
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.99 llvm/lib/Target/X86/X86ISelPattern.cpp:1.100
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.99 Fri Apr 1 23:30:17 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Tue Apr 5 23:21:07 2005
@@ -1818,6 +1818,57 @@
BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1);
return Result;
+ case ISD::MULHU:
+ switch (N.getValueType()) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i8: Tmp2 = X86::MUL8r; break;
+ case MVT::i16: Tmp2 = X86::MUL16r; break;
+ case MVT::i32: Tmp2 = X86::MUL32r; break;
+ }
+ // FALL THROUGH
+ case ISD::MULHS: {
+ unsigned MovOpc, LowReg, HiReg;
+ switch (N.getValueType()) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i8:
+ MovOpc = X86::MOV8rr;
+ LowReg = X86::AL;
+ HiReg = X86::AH;
+ Opc = X86::IMUL8r;
+ break;
+ case MVT::i16:
+ MovOpc = X86::MOV16rr;
+ LowReg = X86::AX;
+ HiReg = X86::DX;
+ Opc = X86::IMUL16r;
+ break;
+ case MVT::i32:
+ MovOpc = X86::MOV32rr;
+ LowReg = X86::EAX;
+ HiReg = X86::EDX;
+ Opc = X86::IMUL32r;
+ break;
+ }
+ if (Node->getOpcode() != ISD::MULHS)
+ Opc = Tmp2; // Get the MULHU opcode.
+
+ Op0 = Node->getOperand(0);
+ Op1 = Node->getOperand(1);
+ if (getRegPressure(Op0) > getRegPressure(Op1)) {
+ Tmp1 = SelectExpr(Op0);
+ Tmp2 = SelectExpr(Op1);
+ } else {
+ Tmp2 = SelectExpr(Op1);
+ Tmp1 = SelectExpr(Op0);
+ }
+
+ // FIXME: Implement folding of loads into the memory operands here!
+ BuildMI(BB, MovOpc, 1, LowReg).addReg(Tmp1);
+ BuildMI(BB, Opc, 1).addReg(Tmp2);
+ BuildMI(BB, MovOpc, 1, Result).addReg(HiReg);
+ return Result;
+ }
+
case ISD::SUB:
case ISD::MUL:
case ISD::AND:
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