[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC32ISelSimple.cpp
Nate Begeman
natebegeman at mac.com
Mon Apr 4 21:23:11 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelPattern.cpp updated: 1.44 -> 1.45
PPC32ISelSimple.cpp updated: 1.132 -> 1.133
---
Log message:
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
---
Diffs of the changes: (+27 -21)
PPC32ISelPattern.cpp | 40 +++++++++++++++++++++++-----------------
PPC32ISelSimple.cpp | 8 ++++----
2 files changed, 27 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.44 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.45
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.44 Mon Apr 4 19:15:08 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Mon Apr 4 23:22:58 2005
@@ -497,17 +497,17 @@
return Count;
}
-/// canUseAsImmediateForOpcode - This method returns a value indicating whether
+/// getImmediateForOpcode - This method returns a value indicating whether
/// the ConstantSDNode N can be used as an immediate to Opcode. The return
/// values are either 0, 1 or 2. 0 indicates that either N is not a
/// ConstantSDNode, or is not suitable for use by that opcode. A return value
/// of 1 indicates that the constant may be used in normal immediate form. A
/// return value of 2 indicates that the constant may be used in shifted
-/// immediate form. If the return value is nonzero, the constant value is
-/// placed in Imm.
+/// immediate form. A return value of 3 indicates that log base 2 of the
+/// constant may be used.
///
-static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
- unsigned& Imm, bool U = false) {
+static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
+ unsigned& Imm, bool U = false) {
if (N.getOpcode() != ISD::Constant) return 0;
int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
@@ -533,7 +533,7 @@
if (!U && (v <= 32767 && v >= -32768)) { Imm = v & 0xFFFF; return 1; }
break;
case ISD::SDIV:
- if (0 != ExactLog2(v)) { Imm = ExactLog2(v); return 1; }
+ if ((Imm = ExactLog2(v))) { return 3; }
break;
}
return 0;
@@ -619,10 +619,10 @@
Opc = getBCCForSetCC(SetCC->getCondition(), U);
Tmp1 = SelectExpr(SetCC->getOperand(0));
- // Pass the optional argument U to canUseAsImmediateForOpcode for SETCC,
+ // Pass the optional argument U to getImmediateForOpcode for SETCC,
// so that it knows whether the SETCC immediate range is signed or not.
- if (1 == canUseAsImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
- Tmp2, U)) {
+ if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
+ Tmp2, U)) {
if (U)
BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
else
@@ -647,7 +647,7 @@
unsigned imm = 0, opcode = N.getOpcode();
if (N.getOpcode() == ISD::ADD) {
Reg = SelectExpr(N.getOperand(0));
- if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, imm)) {
+ if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
offset = imm;
return false;
}
@@ -665,9 +665,15 @@
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
+ // Get the MBB we will fall through to so that we can hand it off to the
+ // branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
+ ilist<MachineBasicBlock>::iterator It = BB;
+ MachineBasicBlock *Fallthrough = ++It;
+
Select(N.getOperand(0)); //chain
unsigned Opc = SelectSetCR0(N.getOperand(1));
- BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(Dest);
+ BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
+ .addMBB(Dest).addMBB(Fallthrough);
return;
}
@@ -1285,7 +1291,7 @@
case ISD::ADD:
assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
Tmp1 = SelectExpr(N.getOperand(0));
- switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
+ switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
default: assert(0 && "unhandled result code");
case 0: // No immediate
Tmp2 = SelectExpr(N.getOperand(1));
@@ -1303,7 +1309,7 @@
case ISD::AND:
case ISD::OR:
Tmp1 = SelectExpr(N.getOperand(0));
- switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
+ switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
default: assert(0 && "unhandled result code");
case 0: // No immediate
Tmp2 = SelectExpr(N.getOperand(1));
@@ -1364,7 +1370,7 @@
return Result;
}
Tmp1 = SelectExpr(N.getOperand(0));
- switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
+ switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
default: assert(0 && "unhandled result code");
case 0: // No immediate
Tmp2 = SelectExpr(N.getOperand(1));
@@ -1382,7 +1388,7 @@
case ISD::SUB:
Tmp2 = SelectExpr(N.getOperand(1));
- if (1 == canUseAsImmediateForOpcode(N.getOperand(0), opcode, Tmp1))
+ if (1 == getImmediateForOpcode(N.getOperand(0), opcode, Tmp1))
BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
else {
Tmp1 = SelectExpr(N.getOperand(0));
@@ -1392,7 +1398,7 @@
case ISD::MUL:
Tmp1 = SelectExpr(N.getOperand(0));
- if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
+ if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
else {
Tmp2 = SelectExpr(N.getOperand(1));
@@ -1402,7 +1408,7 @@
case ISD::SDIV:
case ISD::UDIV:
- if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp3)) {
+ if (3 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp3)) {
Tmp1 = MakeReg(MVT::i32);
Tmp2 = SelectExpr(N.getOperand(0));
BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(Tmp3);
Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.132 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.133
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.132 Wed Mar 30 13:38:35 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp Mon Apr 4 23:22:58 2005
@@ -1585,11 +1585,11 @@
.addImm(0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
- BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
+ BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(PPC::BNE)
.addMBB(MBBMap[BI.getSuccessor(0)])
.addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
- BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
+ BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(PPC::BEQ)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
if (BI.getSuccessor(0) != NextBB)
@@ -1604,7 +1604,7 @@
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
if (BI.getSuccessor(0) != NextBB) {
- BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
+ BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(0)])
.addMBB(MBBMap[BI.getSuccessor(1)]);
if (BI.getSuccessor(1) != NextBB)
@@ -1613,7 +1613,7 @@
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
Opcode = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
- BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
+ BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
.addMBB(MBBMap[BI.getSuccessor(1)])
.addMBB(MBBMap[BI.getSuccessor(0)]);
}
More information about the llvm-commits
mailing list