[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.73 -> 1.74
---
Log message:

FNEG/FABS

---
Diffs of the changes:  (+17 -4)

 AlphaISelPattern.cpp |   21 +++++++++++++++++----
 1 files changed, 17 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.73 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.74
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.73	Fri Apr  1 23:03:19 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Sat Apr  2 13:04:58 2005
@@ -75,10 +75,6 @@
       setOperationAction(ISD::MEMSET           , MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY           , MVT::Other, Expand);
 
-      // We don't support these yet.
-      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
-      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
-
       //Doesn't work yet
       setOperationAction(ISD::SETCC            , MVT::f32,   Promote);
 
@@ -541,6 +537,23 @@
     Node->dump();
     assert(0 && "Node not handled!\n");
 
+  case ISD::FNEG:
+    if(ISD::FABS == N.getOperand(0).getOpcode())
+      {
+	Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+	BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
+      } else {
+	Tmp1 = SelectExpr(N.getOperand(0));
+	Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS ;
+	BuildMI(BB, Opc, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+      }
+    return Result;
+
+  case ISD::FABS:
+    Tmp1 = SelectExpr(N.getOperand(0));
+    BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
+    return Result;
+
   case ISD::SELECT:
     {
       //Tmp1 = SelectExpr(N.getOperand(0)); //Cond