[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp AlphaInstrInfo.td
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Sat Feb 5 05:19:28 PST 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.32 -> 1.33
AlphaInstrInfo.td updated: 1.17 -> 1.18
---
Log message:
added ugly support for fp compares
---
Diffs of the changes: (+71 -23)
AlphaISelPattern.cpp | 84 ++++++++++++++++++++++++++++++++++++++++-----------
AlphaInstrInfo.td | 10 +++---
2 files changed, 71 insertions(+), 23 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.32 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.33
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.32 Fri Feb 4 20:24:26 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Sat Feb 5 07:19:12 2005
@@ -58,12 +58,14 @@
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); //what is the sign expansion of 1? 1 or -1?
- setOperationAction(ISD::SREM, MVT::f32, Expand);
- setOperationAction(ISD::SREM, MVT::f64, Expand);
+ setOperationAction(ISD::SREM , MVT::f32 , Expand);
+ setOperationAction(ISD::SREM , MVT::f64 , Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
- setOperationAction(ISD::MEMSET , MVT::Other, Expand);
- setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
+ setOperationAction(ISD::MEMSET , MVT::Other, Expand);
+ setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
+
+ setOperationAction(ISD::SETCC , MVT::f32 , Promote);
computeRegisterProperties();
@@ -312,6 +314,16 @@
Node->dump();
assert(0 && "Node not handled!\n");
+ case ISD::SELECT:
+ {
+ Tmp1 = SelectExpr(N.getOperand(0)); //Cond
+ Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
+ Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
+ // Get the condition into the zero flag.
+ BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
+ return Result;
+ }
+
case ISD::FP_ROUND:
assert (DestType == MVT::f32 && N.getOperand(0).getValueType() == MVT::f64 && "only f64 to f32 conversion supported here");
Tmp1 = SelectExpr(N.getOperand(0));
@@ -797,7 +809,7 @@
bool isConst1 = false;
bool isConst2 = false;
int dir;
-
+
//Tmp1 = SelectExpr(N.getOperand(0));
if(N.getOperand(0).getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
@@ -862,19 +874,54 @@
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
- }
- }
- else
- {
- Node->dump();
- assert(0 && "only integer");
- }
+ }
+ } else {
+ bool rev = false;
+ bool inv = false;
+
+ switch (SetCC->getCondition()) {
+ default: Node->dump(); assert(0 && "Unknown FP comparison!");
+ case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
+ case ISD::SETLT: Opc = Alpha::CMPTLT; break;
+ case ISD::SETLE: Opc = Alpha::CMPTLE; break;
+ case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
+ case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
+ case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
+ }
+
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ if (rev) std::swap(Tmp1, Tmp2);
+ Tmp3 = MakeReg(MVT::f64);
+ //do the comparison
+ BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+
+ //now arrange for Result (int) to have a 1 or 0
+
+ // Spill the FP to memory and reload it from there.
+ unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
+ MachineFunction *F = BB->getParent();
+ int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
+ unsigned Tmp4 = MakeReg(MVT::f64);
+ BuildMI(BB, Alpha::CVTTQ, 1, Tmp4).addReg(Tmp3);
+ BuildMI(BB, Alpha::STT, 3).addReg(Tmp4).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ unsigned Tmp5 = MakeReg(MVT::i64);
+ BuildMI(BB, Alpha::LDQ, 2, Tmp5).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+
+ //now, set result based on Tmp5
+ //Set Tmp6 if fp cmp was false
+ unsigned Tmp6 = MakeReg(MVT::i64);
+ BuildMI(BB, Alpha::CMPEQ, 2, Tmp6).addReg(Tmp5).addReg(Alpha::R31);
+ //and invert
+ BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Tmp6).addReg(Alpha::R31);
+
+ }
+// else
+// {
+// Node->dump();
+// assert(0 && "Not a setcc in setcc");
+// }
}
- else
- {
- Node->dump();
- assert(0 && "Not a setcc in setcc");
- }
return Result;
}
@@ -1101,7 +1148,8 @@
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
- Select(N.getOperand(0));
+ Select(N.getOperand(0)); //chain
+
Tmp1 = SelectExpr(N.getOperand(1));
BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
return;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.17 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.18
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.17 Fri Feb 4 14:25:52 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Sat Feb 5 07:19:12 2005
@@ -224,6 +224,11 @@
def CMPULT : OForm< 0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "CMPULT $RA,$RB,$RC">; //Compare unsigned quadword less than
def CMPULTi : OFormL<0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "CMPULT $RA,$L,$RC">; //Compare unsigned quadword less than
+//Comparison, FP
+def CMPTEQ : FPForm<0x16, 0x0A5, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmpteq $RA,$RB,$RC">; //Compare T_floating equal
+def CMPTLE : FPForm<0x16, 0x0A7, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptle $RA,$RB,$RC">; //Compare T_floating less than or equal
+def CMPTLT : FPForm<0x16, 0x0A6, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptlt $RA,$RB,$RC">; //Compare T_floating less than
+def CMPTUN : FPForm<0x16, 0x0A4, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptun $RA,$RB,$RC">; //Compare T_floating unordered
//There are in the Multimedia extentions, so let's not use them yet
def MAXSB8 : OForm<0x1C, 0x3E, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
@@ -363,11 +368,6 @@
//WH64 Mfc 18.F800 Write hint 64 bytes
//WMB Mfc 18.4400 Write memory barrier
-//CMPTEQ F-P 16.0A5 Compare T_floating equal
-//CMPTLE F-P 16.0A7 Compare T_floating less than or equal
-//CMPTLT F-P 16.0A6 Compare T_floating less than
-//CMPTUN F-P 16.0A4 Compare T_floating unordered
-
//FCMOVEQ F-P 17.02A FCMOVE if = zero
//FCMOVGE F-P 17.02D FCMOVE if >= zero
//FCMOVGT F-P 17.02F FCMOVE if > zero
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