[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.80 -> 1.81
---
Log message:

Fix a problem where were were literally selecting for INCREASED register 
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.


---
Diffs of the changes:  (+8 -8)

Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.80 llvm/lib/Target/X86/X86ISelPattern.cpp:1.81
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.80	Wed Jan 19 02:07:05 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Wed Jan 19 11:24:34 2005
@@ -1185,11 +1185,11 @@
         } else if (RegSize != 8) {
           unsigned AReg, BReg;
           if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
-            AReg = SelectExpr(ShrVal);
             BReg = SelectExpr(ShlVal);
+            AReg = SelectExpr(ShrVal);
           } else {
-            BReg = SelectExpr(ShlVal);
             AReg = SelectExpr(ShrVal);
+            BReg = SelectExpr(ShlVal);
           }
           unsigned ShAmt = SelectExpr(ShrAmt);
           BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
@@ -1221,11 +1221,11 @@
         } else if (RegSize != 8) {
           unsigned AReg, BReg;
           if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
-            AReg = SelectExpr(ShrVal);
-            BReg = SelectExpr(ShlVal);
+            AReg = SelectExpr(ShlVal);
+            BReg = SelectExpr(ShrVal);
           } else {
-            BReg = SelectExpr(ShlVal);
-            AReg = SelectExpr(ShrVal);
+            BReg = SelectExpr(ShrVal);
+            AReg = SelectExpr(ShlVal);
           }
           unsigned ShAmt = SelectExpr(ShlAmt);
           BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
@@ -1250,11 +1250,11 @@
           } else if (RegSize != 8) {
             unsigned AReg, BReg;
             if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
-              AReg = SelectExpr(ShrVal);
               BReg = SelectExpr(ShlVal);
+              AReg = SelectExpr(ShrVal);
             } else {
-              BReg = SelectExpr(ShlVal);
               AReg = SelectExpr(ShrVal);
+              BReg = SelectExpr(ShlVal);
             }
             unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
             BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)