[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.58 -> 1.59
---
Log message:

Do not codegen 'xor bool, true' as 'not reg'.  not reg inverts the upper bits
of the bytereg.  This fixes yacr2, 300.twolf and probably others.


---
Diffs of the changes:  (+7 -4)

Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.58 llvm/lib/Target/X86/X86ISelPattern.cpp:1.59
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.58	Sun Jan 16 18:00:33 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Sun Jan 16 18:23:16 2005
@@ -1585,16 +1585,19 @@
 
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
       if (CN->isAllOnesValue() && Node->getOpcode() == ISD::XOR) {
+        Opc = 0;
         switch (N.getValueType()) {
         default: assert(0 && "Cannot add this type!");
-        case MVT::i1:
+        case MVT::i1:  break;  // Not supported, don't invert upper bits!
         case MVT::i8:  Opc = X86::NOT8r;  break;
         case MVT::i16: Opc = X86::NOT16r; break;
         case MVT::i32: Opc = X86::NOT32r; break;
         }
-        Tmp1 = SelectExpr(Op0);
-        BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
-        return Result;
+        if (Opc) {
+          Tmp1 = SelectExpr(Op0);
+          BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+          return Result;
+        }
       }
 
       switch (N.getValueType()) {