[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9RegisterInfo.td updated: 1.3 -> 1.4
---
Log message:

Revamp the Register class, and allow the use of the RegisterGroup class to
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!


---
Diffs of the changes:  (+17 -9)

Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.3 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.4
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td:1.3	Sat Aug 21 15:13:09 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td	Mon Sep 13 23:16:49 2004
@@ -12,19 +12,27 @@
 //===----------------------------------------------------------------------===//
 
 // Ri - One of the 32 64 bit integer registers
-class Ri<bits<5> num> : Register {
+class Ri<bits<5> num, string n> : Register<n> {
   field bits<5> Num = num;        // Numbers are identified with a 5 bit ID
 }
 
 let Namespace = "SparcV9" in {
-  def G0 : Ri< 0>;    def G1 : Ri< 1>;    def G2 : Ri< 2>;    def G3 : Ri< 3>;
-  def G4 : Ri< 4>;    def G5 : Ri< 5>;    def G6 : Ri< 6>;    def G7 : Ri< 7>;
-  def O0 : Ri< 8>;    def O1 : Ri< 9>;    def O2 : Ri<10>;    def O3 : Ri<11>;
-  def O4 : Ri<12>;    def O5 : Ri<13>;    def O6 : Ri<14>;    def O7 : Ri<15>;
-  def L0 : Ri<16>;    def L1 : Ri<17>;    def L2 : Ri<18>;    def L3 : Ri<19>;
-  def L4 : Ri<20>;    def L5 : Ri<21>;    def L6 : Ri<22>;    def L7 : Ri<23>;
-  def I0 : Ri<24>;    def I1 : Ri<25>;    def I2 : Ri<26>;    def I3 : Ri<27>;
-  def I4 : Ri<28>;    def I5 : Ri<29>;    def I6 : Ri<30>;    def I7 : Ri<31>;
+  def G0 : Ri< 0, "G0">;    def G1 : Ri< 1, "G1">;
+  def G2 : Ri< 2, "G2">;    def G3 : Ri< 3, "G3">;
+  def G4 : Ri< 4, "G4">;    def G5 : Ri< 5, "G5">;
+  def G6 : Ri< 6, "G6">;    def G7 : Ri< 7, "G7">;
+  def O0 : Ri< 8, "O0">;    def O1 : Ri< 9, "O1">;
+  def O2 : Ri<10, "O2">;    def O3 : Ri<11, "O3">;
+  def O4 : Ri<12, "O4">;    def O5 : Ri<13, "O5">;
+  def O6 : Ri<14, "O6">;    def O7 : Ri<15, "O7">;
+  def L0 : Ri<16, "L0">;    def L1 : Ri<17, "L1">; 
+  def L2 : Ri<18, "L2">;    def L3 : Ri<19, "L3">;
+  def L4 : Ri<20, "L4">;    def L5 : Ri<21, "L5">;
+  def L6 : Ri<22, "L6">;    def L7 : Ri<23, "L7">;
+  def I0 : Ri<24, "I0">;    def I1 : Ri<25, "I1">;
+  def I2 : Ri<26, "I2">;    def I3 : Ri<27, "I3">;
+  def I4 : Ri<28, "I4">;    def I5 : Ri<29, "I5">;
+  def I6 : Ri<30, "I6">;    def I7 : Ri<31, "I7">;
   // Floating-point registers?
   // ...
 }