[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp PowerPCRegisterInfo.h PowerPCRegisterInfo.td
Misha Brukman
brukman at cs.uiuc.edu
Wed Aug 11 16:45:05 PDT 2004
Changes in directory llvm/lib/Target/PowerPC:
PowerPCRegisterInfo.cpp updated: 1.26 -> 1.27
PowerPCRegisterInfo.h updated: 1.2 -> 1.3
PowerPCRegisterInfo.td updated: 1.8 -> 1.9
---
Log message:
* Set the is64bit boolean flag in PowerPCRegisterInfo
* Doubles are 8 bytes in 64-bit PowerPC, and use the general register class
* Use double-word loads and stores for restoring from/saving to stack
* Do not allocate R2 if compiling for AIX
---
Diffs of the changes: (+30 -18)
Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp:1.26 llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp:1.27
--- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp:1.26 Tue Aug 10 17:47:03 2004
+++ llvm/lib/Target/PowerPC/PowerPCRegisterInfo.cpp Wed Aug 11 18:44:55 2004
@@ -30,9 +30,14 @@
#include <iostream>
using namespace llvm;
-PowerPCRegisterInfo::PowerPCRegisterInfo()
- : PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN,
- PPC::ADJCALLSTACKUP) {}
+namespace llvm {
+ // Switch toggling compilation for AIX
+ extern cl::opt<bool> AIX;
+}
+
+PowerPCRegisterInfo::PowerPCRegisterInfo(bool is64b)
+ : PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+ is64bit(is64b) {}
static unsigned getIdx(const TargetRegisterClass *RC) {
if (RC == PowerPC::GPRCRegisterClass) {
@@ -41,12 +46,13 @@
case 1: return 0;
case 2: return 1;
case 4: return 2;
+ case 8: return 3;
}
} else if (RC == PowerPC::FPRCRegisterClass) {
switch (RC->getSize()) {
default: assert(0 && "Invalid data size!");
- case 4: return 3;
- case 8: return 4;
+ case 4: return 4;
+ case 8: return 5;
}
}
std::cerr << "Invalid register class to getIdx()!\n";
@@ -59,7 +65,7 @@
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] = {
- PPC::STB, PPC::STH, PPC::STW, PPC::STFS, PPC::STFD
+ PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
};
unsigned OC = Opcode[getIdx(RC)];
if (SrcReg == PPC::LR) {
@@ -78,7 +84,7 @@
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] = {
- PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
+ PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
};
unsigned OC = Opcode[getIdx(RC)];
if (DestReg == PPC::LR) {
@@ -221,17 +227,19 @@
// adjust stack pointer: r1 -= numbytes
if (NumBytes <= 32768) {
- MI = BuildMI(PPC::STWU, 3).addReg(PPC::R1).addSImm(-NumBytes)
+ unsigned StoreOpcode = is64bit ? PPC::STDU : PPC::STWU;
+ MI = BuildMI(StoreOpcode, 3).addReg(PPC::R1).addSImm(-NumBytes)
.addReg(PPC::R1);
MBB.insert(MBBI, MI);
} else {
int NegNumbytes = -NumBytes;
+ unsigned StoreOpcode = is64bit ? PPC::STDUX : PPC::STWUX;
MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
MBB.insert(MBBI, MI);
MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
.addImm(NegNumbytes & 0xFFFF);
MBB.insert(MBBI, MI);
- MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
+ MI = BuildMI(StoreOpcode, 3).addReg(PPC::R1).addReg(PPC::R1)
.addReg(PPC::R0);
MBB.insert(MBBI, MI);
}
@@ -249,7 +257,8 @@
unsigned NumBytes = MFI->getStackSize();
if (NumBytes != 0) {
- MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
+ unsigned Opcode = is64bit ? PPC::LD : PPC::LWZ;
+ MI = BuildMI(Opcode, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
MBB.insert(MBBI, MI);
}
}
@@ -259,9 +268,10 @@
const TargetRegisterClass*
PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
switch (Ty->getTypeID()) {
- case Type::LongTyID:
- case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
default: assert(0 && "Invalid type to getClass!");
+ case Type::LongTyID:
+ case Type::ULongTyID:
+ if (!is64bit) assert(0 && "Long values can't fit in registers!");
case Type::BoolTyID:
case Type::SByteTyID:
case Type::UByteTyID:
@@ -270,7 +280,7 @@
case Type::IntTyID:
case Type::UIntTyID:
case Type::PointerTyID: return &GPRCInstance;
-
+
case Type::FloatTyID:
case Type::DoubleTyID: return &FPRCInstance;
}
Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.2 llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.3
--- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h:1.2 Tue Jul 27 13:38:40 2004
+++ llvm/lib/Target/PowerPC/PowerPCRegisterInfo.h Wed Aug 11 18:44:55 2004
@@ -21,8 +21,10 @@
class Type;
-struct PowerPCRegisterInfo : public PowerPCGenRegisterInfo {
- PowerPCRegisterInfo();
+class PowerPCRegisterInfo : public PowerPCGenRegisterInfo {
+ bool is64bit;
+public:
+ PowerPCRegisterInfo(bool is64b);
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
/// Code Generation virtual methods...
Index: llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.8 llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.9
--- llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td:1.8 Tue Aug 10 17:47:03 2004
+++ llvm/lib/Target/PowerPC/PowerPCRegisterInfo.td Wed Aug 11 18:44:55 2004
@@ -77,13 +77,13 @@
// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
def GPRC :
RegisterClass<i32, 4,
- [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
+ [R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
- R16, R15, R14, R13, R0, R1, LR]>
+ R16, R15, R14, R13, R0, R2, R1, LR]>
{
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
- return end()-3;
+ return end() - (AIX ? 4 : 3);
}
}];
}
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