[llvm-commits] CVS: llvm/lib/Target/X86/Makefile

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

Makefile updated: 1.17 -> 1.18

---
Log message:

Factor a bunch of the rules and add support for generating the asmwriter.


---
Diffs of the changes:  (+23 -21)

Index: llvm/lib/Target/X86/Makefile
diff -u llvm/lib/Target/X86/Makefile:1.17 llvm/lib/Target/X86/Makefile:1.18
--- llvm/lib/Target/X86/Makefile:1.17	Thu Jul 22 16:30:35 2004
+++ llvm/lib/Target/X86/Makefile	Sun Aug  1 01:01:32 2004
@@ -10,42 +10,44 @@
 LIBRARYNAME = x86
 include $(LEVEL)/Makefile.common
 
+TARGET = X86
+
 # Make sure that tblgen is run, first thing.
 $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
                  X86GenRegisterInfo.inc X86GenInstrNames.inc \
-                 X86GenInstrInfo.inc X86GenInstrSelector.inc
+                 X86GenInstrInfo.inc X86GenAsmWriter.inc \
+                 X86GenInstrSelector.inc
+
+TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
+          $(SourceDir)/../Target.td
 
-X86GenRegisterNames.inc::  $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
-                           $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td register names with tblgen"
+$(TARGET)GenRegisterNames.inc::  $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td register names with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
 
-X86GenRegisterInfo.h.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
-                           $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td register information header with tblgen"
+$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td register information header with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
 
-X86GenRegisterInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86RegisterInfo.td \
-                         $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td register information implementation with tblgen"
+$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td register info implementation with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
 
-X86GenInstrNames.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
-                       $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td instruction names with tblgen"
+$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td instruction names with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
 
-X86GenInstrInfo.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
-                      $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td instruction information with tblgen"
+$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td instruction information with tblgen"
 	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
 
-X86GenInstrSelector.inc:: $(SourceDir)/X86.td $(SourceDir)/X86InstrInfo.td \
-                          $(SourceDir)/../Target.td $(TBLGEN)
-	@echo "Building X86.td instruction selector with tblgen"
-	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
-
+$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td assembly writer with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
 
+$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
+	@echo "Building $(TARGET).td instruction selector with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
 
 clean::
 	$(VERB) rm -f *.inc